Xilinx Virtex-4 ML461 User Manual page 45

Memory interfaces
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R
current can be measured for each of these power planes. The current measurement for each
design running on the ML461 is shown in
Before each measurement was taken, the design was verified to be running without error
at the listed frequency using the ChipScope™ analyzer. The VTT and VREF power for
SSTL18, SSTL2, and HSTL standards are derived from their corresponding VDD power so
separate power usage for these power planes is not available.
The measured current usage is shown in
Table 4-5: Measured Current Usage
Configuration Image
Initial Power-Up
All FPGAs with Blank Design
DDR1 Registered DIMM, 72-bit
Design
DDR2 Registered DIMM, 144-bit
Design
DDR2 Registered DIMM, 72-bit
Design using SSTL18_II_DCI for DQ
and ODT on DDR2 Memory
DDR2 Registered DIMM 144-bit
Design using SSTL18_II_DCI for DQ
QDR2 72-bit Design
RLDRAM II 36-bit Design
After the current has been measured, the power is calculated by multiplying the current
supplying the power plane by the voltage level of that power plane. The power
consumption is shown in
The measured power consumption is shown in
Table 4-6: Measured Power Consumption
Configuration Image
Initial Power-Up
All FPGAs with Blank Design
DDR1 Registered DIMM
72-bit Design
DDR2 Registered DIMM
144-bit Design
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Frequency
(MHz)
1.2V
n/a
0
n/a
400
200
900
267
1700
267
1100
267
1700
300
1100
267
900
Table
4-6.
Freq
(MHz)
1.2V
2.5V
3.3V
n/a
0.00
6.50
n/a
0.48
1.75
200
1.08
3.00
267
2.04
4.50
www.xilinx.com
Power Measurements on the ML461
Table
4-5.
Table
4-5.
Power Plane Current Usage (mA)
SSTL18
2.5V
3.3V
2600
600
700
600
1200
800
1800
600
1300
600
1800
600
1200
700
1100
600
Table
4-6.
Power Consumption (Watts)
SSTL18
SSTL2
1.8V
2.6V
1.98
1.62
2.60
1.98
1.62
2.86
2.64
1.62
8.06
1.98
9.00
2.86
SSTL2
HSTL
1.8V
2.6V
1.8V
900
1000
100
900
1100
100
900
3100
100
5000
1100
100
4600
1100
100
7300
1100
100
1700
1100
1000
1100
1100
700
HSTL
TOTAL
Design
1.8V
0.18
12.88
4.01
0.18
8.87
0.18
16.58
9.93
0.18
20.56
13.91
45

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