Board Design Considerations - Xilinx Virtex-4 ML461 User Manual

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Board Design Considerations

The Virtex-4 ML461 Development Board design allows for DCI termination to each of the
memory interfaces on the board. A preliminary analysis of the Weighted Average
Simultaneously Switching Outputs (WASSO) for all four Virtex-4 FPGA devices indicates
that the SSO guidelines are met for the current pinout. Occasionally, for banks with more
outputs than supported by WASSO analysis, additional pins are used to provide
complimentary outputs to compensate for the switching guidelines. As a back-up plan, to
protect against any power-related issues due to exclusive use of DCI termination, external
terminations at both the memory and FPGA are also provided for all data signals for all
memory interfaces on the current version of the Virtex-4 ML461 Development Board.
There are two choices of terminations for the memory interfaces:
1.
2.
Simulation results show no performance difference between these two schemes, and the
power usage for the split termination scheme is much higher than the V
Thus, the termination of choice for Data and Strobe signals throughout the Virtex-4 ML461
Development Board is the V
termination. See
specific recommendations and guidelines for terminations.
For a fully configured DCI implementation, these external terminations can be
depopulated. These are V
SSTL18, and HSTL signals.
The current implementation of the direct clocking method for data capture delays all data
bits associated with a given strobe signal by the same number of taps using the IDELAY
controller. This imposes a requirement on the board layout such that the trace delay for a
strobe and the corresponding data bits are matched up to the pad of the die of the Virtex-4
device. So the sum of board trace delay and pad-to-pin flight delay are matched for each
group of such data/strobe signals.
The physical dimensions of the raw PCB board is 12 inches x 12 inches. With the overhangs
due to edge connectors, the actual size of the fully assembled board is approximately
12.5 inches x 13 inches, with 1.5 inches height allowance for the DIMM modules. This is an
18-layer board with eight signal layers and 10 power planes and uses NELCO 4013
material.
Refer to UG072: Virtex-4 PCB Designer's Guide for more information on the Printed Circuit
Board design using Virtex-4 devices.
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
A split termination with a pair of 100Ω resistors between V
A V termination with a single 50Ω termination to the V
TT
TT
Chapter 5, "Signal Integrity Recommendations and Simulations,"
terminations to the respective voltage levels for SSTL2,
TT
Figure 3-10 shows a stack-up diagram of the ML461 Revision B PCB.
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termination. Address and Control signals also have V
Board Design Considerations
and GND.
DD
level.
REF
termination.
TT
for
TT
33