Fpga #4 Pinout - Xilinx Virtex-4 ML461 User Manual

Appendix A: FPGA Pinouts

FPGA #4 Pinout

Table A-4
Table A-4: FPGA #4 Pinout
Signal Name
RLD2_A0
RLD2_A1
RLD2_A2
RLD2_A3
RLD2_A4
RLD2_A5
RLD2_A6
RLD2_A7
RLD2_A8
RLD2_A9
RLD2_A10
RLD2_A11
RLD2_A12
RLD2_A13
RLD2_A14
RLD2_A15
RLD2_A16
RLD2_A17
RLD2_A18
RLD2_A19
RLD2_BA0
RLD2_BA1
RLD2_BA2
RLD2_CS_BY0_1_N
RLD2_CS_BY2_3_N
RLD2_DM_BY0_1_N
RLD2_DM_BY2_3_N
RLD2_REF_N
RLD2_QVLD_BY0_1
76
lists the connections for FPGA #4 (U33).
Pin
RLDRAM II Memory Interface
A22 RLD2_QVLD_BY2_3
A21 RLD2_WE_N
D24 RLD2_READ_VALID
C24 RLD2_READ_VALID
G19 RLD2_CK_BY0_1_P
F19 RLD2_CK_BY0_1_N
E23 RLD2_DK_BY0_1_P
E22 RLD2_DK_BY0_1_N
F20 RLD2_CK_BY2_3_P
E20 RLD2_CK_BY2_3_N
D23 RLD2_DK_BY2_3_P
C23 RLD2_DK_BY2_3_N
H20 RLD2_QK_BY0_P
G20 RLD2_QK_BY0_N
F26 RLD2_QK_BY1_P
E26 RLD2_QK_BY1_N
H24 RLD2_QK_BY2_P
H23 RLD2_QK_BY2_N
G26 RLD2_QK_BY3_P
G25 RLD2_QK_BY3_N
H22 RLD2_DQ_BY0_B0
H21 RLD2_DQ_BY0_B1
E25 RLD2_DQ_BY0_B2
H5 RLD2_DQ_BY0_B3
G2 RLD2_DQ_BY0_B4
H4 RLD2_DQ_BY0_B5
H3 RLD2_DQ_BY0_B6
H6 RLD2_DQ_BY0_B7
A5 RLD2_DQ_BY0_B8
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
B21
G1
C4
D4
E3
E2
D2
D1
F24
F23
D26
D25
B6
C6
G10
G9
A24
A23
G18
G17
D10
C10
D9
C8
A8
A7
F10
E10
A6