Xilinx DK-V7-VC709-G User Manual
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Xilinx DK-V7-VC709-G User Manual

Xilinx DK-V7-VC709-G User Manual

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VC709 Evaluation
Board for the
Virtex-7 FPGA
User Guide
UG887 (v1.4) December 4, 2014

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Summary of Contents for Xilinx DK-V7-VC709-G

  • Page 1 VC709 Evaluation Board for the Virtex-7 FPGA User Guide UG887 (v1.4) December 4, 2014...

  • Page 2: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 3 1-20. Added PCIe® edge connector information after Table 1-12. Updated description for XADC_GPIO_3, 2, 1, 0 in Table 1-25. Updated Table A-3 added Figure A-3. Updated VC709 Board XDC Listing. Updated References. UG887 (v1.4) December 4, 2014 www.xilinx.com VC709 Evaluation Board...
  • Page 4 VC709 Evaluation Board www.xilinx.com UG887 (v1.4) December 4, 2014...

  • Page 5: Table Of Contents

    ........97 VC709 Evaluation Board www.xilinx.com Send Feedback...
  • Page 6 Appendix F: Additional Resources Xilinx Resources ............101 Solution Centers .

  • Page 7: Chapter 1: Vc709 Evaluation Board Features

    SMA connectors (one pair for MGT_REFCLK) • PCI Express (eight lanes) • 4 X Small form-factor pluggable plus (SFP+) connectors • PCI Express endpoint connectivity • Gen1 8-lane (x8) VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 8 Power management • PMBus voltage and current monitoring through TI power controllers • XADC header • Configuration options • Linear BPI flash memory • USB JTAG (Digilent) configuration port www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 9 1 KB EEPROM DIP Switch SW11 JTAG Interface USB-to-UART Config and Micro-B USB 4X SFP+ Cage Bridge C Bus Switch Flash Addr Connector UG887_c1_01_012113 Figure 1-1: VC709 Board Block Diagram VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 10: Feature Descriptions

    System clock, 200 MHz, LVDS (back side of SiTime board) SIT9102-243N25E200.0000 C programmable user clock LVDS, Silicon Labs 156.250 MHz default frequency (back side of SI570BAB0000544DG (I²C 0x5D) board) www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 11 SW12 Power on/off slide switch C and K 1201M2S3AQE2 FMC HPC connector Samtec ASP_134486_01 18–21 Xilinx XADC header 2 x 10 0.1-inch male header INIT LED, dual color Red/Green Avago HSMF-C155 DS10, DS14, Power ON and Power GOOD LEDs Lumex SML-LX0603GW DS16–DS18...

  • Page 12: Virtex-7 Xc7Vx690T-2Ffg1761C Fpga

    Bus Width CCLK Direction Settings (M[2:0]) Master BPI x8, x16 Output JTAG Not applicable For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide (UG470) [Ref www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 13 1.5V Bank 33 VCC1V5_FPGA 1.5V Bank 34 VCC1V8_FPGA 1.8V Bank 35 VADJ_FPGA 1.8V Bank 36 FMC1_VIO_B_M2C Variable Bank 37 VCC1V5_FPGA 1.5V Bank 38 VCC1V5_FPGA 1.5V Bank 39 VCC1V5_FPGA 1.5V VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 14: Dual Ddr3 Memory Sodimms

    SSTL15 DDR3_A_A7 SSTL15 DDR3_A_A8 SSTL15 DDR3_A_A9 SSTL15 DDR3_A_A10 SSTL15 A10/AP DDR3_A_A11 SSTL15 DDR3_A_A12 SSTL15 A12_BC_N DDR3_A_A13 SSTL15 DDR3_A_A14 SSTL15 DDR3_A_A15 SSTL15 DDR3_A_BA0 SSTL15 DDR3_A_BA1 SSTL15 DDR3_A_BA2 SSTL15 DDR3_A_D0 SSTL15 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 15 SSTL15 DQ23 DDR3_A_D24 SSTL15 DQ24 DDR3_A_D25 SSTL15 DQ25 DDR3_A_D26 SSTL15 DQ26 DDR3_A_D27 SSTL15 DQ27 DDR3_A_D28 SSTL15 DQ28 DDR3_A_D29 SSTL15 DQ29 DDR3_A_D30 SSTL15 DQ30 DDR3_A_D31 SSTL15 DQ31 DDR3_A_D32 SSTL15 DQ32 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 16 DDR3_A_D55 SSTL15 DQ55 DDR3_A_D56 SSTL15 DQ56 DDR3_A_D57 SSTL15 DQ57 DDR3_A_D58 SSTL15 DQ58 DDR3_A_D59 SSTL15 DQ59 DDR3_A_D60 SSTL15 DQ60 DDR3_A_D61 SSTL15 DQ61 DDR3_A_D62 SSTL15 DQ62 DDR3_A_D63 SSTL15 DQ63 DDR3_A_DM0 SSTL15 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 17 DIFF_SSTL15 DQS7_P DDR3_A_CLK0_N DIFF_SSTL15 CK0_N DDR3_A_CLK0_P DIFF_SSTL15 CK0_P DDR3_A_CLK1_N DIFF_SSTL15 CK1_N DDR3_A_CLK1_P DIFF_SSTL15 CK1_P DDR3_A_CKE0 SSTL15 CKE0 DDR3_A_CKE1 SSTL15 CKE1 DDR3_A_RAS_B SSTL15 RAS_B DDR3_A_WE_B SSTL15 WE_B DDR3_A_CAS_B SSTL15 CAS_B VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 18 SSTL15 A12_BC_N AK17 DDR3_B_A13 SSTL15 AM19 DDR3_B_A14 SSTL15 AL19 DDR3_B_A15 SSTL15 AR17 DDR3_B_BA0 SSTL15 AR18 DDR3_B_BA1 SSTL15 AN18 DDR3_B_BA2 SSTL15 AN24 DDR3_B_D0 SSTL15 AM24 DDR3_B_D1 SSTL15 AR22 DDR3_B_D2 SSTL15 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 19 DQ27 AY25 DDR3_B_D28 SSTL15 DQ28 BA25 DDR3_B_D29 SSTL15 DQ29 BB21 DDR3_B_D30 SSTL15 DQ30 BA21 DDR3_B_D31 SSTL15 DQ31 AY14 DDR3_B_D32 SSTL15 DQ32 AW15 DDR3_B_D33 SSTL15 DQ33 BB14 DDR3_B_D34 SSTL15 DQ34 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 20 AP11 DDR3_B_D59 SSTL15 DQ59 AM13 DDR3_B_D60 SSTL15 DQ60 AN13 DDR3_B_D61 SSTL15 DQ61 AM11 DDR3_B_D62 SSTL15 DQ62 AN11 DDR3_B_D63 SSTL15 DQ63 AT22 DDR3_B_DM0 SSTL15 AL22 DDR3_B_DM1 SSTL15 AU24 DDR3_B_DM2 SSTL15 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 21 CK1_N AW17 DDR3_B_CKE0 SSTL15 CKE0 AW18 DDR3_B_CKE1 SSTL15 CKE1 AV19 DDR3_B_RAS_B SSTL15 RAS_B AU19 DDR3_B_WE_B SSTL15 WE_B AT20 DDR3_B_CAS_B SSTL15 CAS_B AT16 DDR3_B_ODT0 SSTL15 ODT0 AW16 DDR3_B_ODT1 SSTL15 ODT1 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 22: Linear Bpi Flash Memory

    80 MHz data rate supported by the flash memory by using a configuration bitstream generated with BitGen options for synchronous configuration. The fastest configuration method uses the external 80 MHz oscillator connected to the FPGA EMCCLK pin. www.xilinx.com VC709 Evaluation Board Send Feedback...
  • Page 23 FLASH_A17 LVCMOS18 BA42 FLASH_A18 LVCMOS18 AU42 FLASH_A19 LVCMOS18 AT41 FLASH_A20 LVCMOS18 BA39 FLASH_A21 LVCMOS18 BA39 FLASH_A22 LVCMOS18 BB39 FLASH_A23 LVCMOS18 AW42 FLASH_A24 LVCMOS18 AW41 FLASH_A25 LVCMOS18 AM36 FLASH_D0 LVCMOS18 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 24 7 Series FPGAs Configuration User Guide (UG470) [Ref The configuration section of 7 Series FPGAs Configuration User Guide (UG470) [Ref 2] provides details on the Master BPI configuration mode. www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 25 FLASH_WAIT_R FLASH_A23 WAIT FLASH_A24 FPGA_CCLK FLASH_A25 RFU1 VCCQ1 RFU2 VCCQ2 1.8V RFU3 VCCQ3 VSS0 VSS1 1.8V VCC1 VSS2 VSS3 VCC2 UG887_c1_04_101514 Figure 1-4: 128 MB Linear Flash Memory (U3) VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 26: Usb Jtag

    FPGA using the Xilinx tools. In addition, the JTAG connector allows debug tools or a software debugger to access the FPGA. The Xilinx tools can also indirectly program the linear BPI flash memory. To accomplish this, the Xilinx tools configure the FPGA with a temporary design to access and program the BPI memory device.

  • Page 27: Clock Generation

    SN74AVC1T45 Voltage Translator UG855_c1_06_101714 Figure 1-6: JTAG Circuit Clock Generation The VC709 board provides six clock sources for the FPGA. Table 1-7 lists the source devices for each clock. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 28 SiT9122 2.5V LVDS 233.33 Memory clock Memory Clock (SYSCLK_233_P and SYSCLK_233_N), page SiT8103 LVCMOS single-ended, 80 MHz, fixed-frequency oscillator (Si Time). See FPGA EMCC clock FPGA EMCC Clock, page www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 29 One possible I/O standard for the FPGA design clock input is: NET "sysclk_p" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank 38 MRCC input NET "sysclk_n" LOC = "G18" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff. Rterm R2 DNP VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 30 156.250 MHz. • Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz – 810 MHz) • PPM frequency jitter: 50 ppm • Differential output • C address 0x5D www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 31 1.8V differential clock circuit is shown in Figure 1-9. X-Ref Target - Figure 1-9 USER_SMA_CLOCK_P Connector USER_SMA_CLOCK_N Connector UG887_c1_09_090612 Figure 1-9: User SMA Clock Source VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 32 The clock outputs are disabled during reset. The part must be programmed after a reset or power-on to get a clock output. The reset pin 1 has a weak internal pull-up. www.xilinx.com VC709 Evaluation Board Send Feedback...

  • Page 33: Memory Clock (Sysclk_233_P And Sysclk_233_N)

    SYSCLK_233_P and SYSCLK_233_N. The P and N signals are connected to FPGA U1 pins AY18 and AY17 respectively. • Oscillator: Si Time SIT9122AC-2D3-25E233.333333 (233.3333 MHz) • PPM frequency jitter: 50 ppm • Differential output VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 34: Fpga Emcc Clock

    FPGA EMCCLK clock input pin AP37 on bank 14. This 80 MHz single-ended signal is named FPGA_EMCCLK. • Oscillator: Si Time SIT8103AC-23-18E-80.0000Y • PPM frequency jitter: 50 ppm • Single-ended 1.8V LVCMOS output www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 35: Gth Transceivers

    Quad 114: • MGTREFCLK0 - No clock • MGTREFCLK1 - No clock • Contains 4 GTH transceivers for PCIe lanes 4–7 • Quad 115: • MGTREFCLK0 - No clock VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 36 Si5324 jitter attenuator MGTREFCLK1 SMA_MGT_REFCLK MGT_BANK_114 GTHE2_CHANNEL_X1Y19 PCIe4 GTHE2_CHANNEL_X1Y18 PCIe5 GTHE2_CHANNEL_X1Y17 PCIe6 GTHE2_CHANNEL_X1Y16 PCIe7 MGTREFCLK0 MGTREFCLK1 MGT_BANK_115 GTHE2_CHANNEL_X1Y23 PCIe0 GTHE2_CHANNEL_X1Y22 PCIe1 GTHE2_CHANNEL_X1Y21 PCIe2 GTHE2_CHANNEL_X1Y20 PCIe3 MGTREFCLK0 MGTREFCLK1 PCIe_CLK MGT_BANK_117 GTHE2_CHANNEL_X1Y31 GTHE2_CHANNEL_X1Y30 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 37 GTHE2_CHANNEL_X1Y37 FMC1 HPC DP1 GTHE2_CHANNEL_X1Y36 FMC1 HPC DP0 MGTREFCLK0 MGTREFCLK1 For more information on the GTH transceivers see 7 Series FPGAs GTX/GTH Transceivers UG476 ) User Guide ( [Ref VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 38: Pci Express Endpoint Connectivity

    1-15). The default lane size selection is 1-lane (J49 pins 1 and 2 jumpered). X-Ref Target - Figure 1-15 PCIE_PRSNT_B PCIE_PRSNT_X1 PCIE_PRSNT_X4 PCIE_PRSNT_X8 UG887_c1_14_083112 Figure 1-15: PCI Express Lane Size Select Jumper J49 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 39 GTHE2_CHANNEL_X1Y16 PCIE_RX7_P PETp7 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y16 PCIE_RX7_N PETn7 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y23 PCIE_TX0_P PERp0 transmit pair Integrated Endpoint block GTHE2_CHANNEL_X1Y23 PCIE_TX0_N PERn0 transmit pair VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 40 PCIE_CLK_Q0_P REFCLK+ differential clock pair from PCIe Integrated Endpoint block MGT_BANK_115 PCIE_CLK_Q0_N REFCLK- differential clock pair from PCIe J49 Lane Size Select PCIE_PRSNT_B J49 2, 4, 6 PRSNT#1 jumper www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 41 GTHE2_CHANNEL_X1Y22 MGTXTXP3_115_W2 PCIE_TX0_P PERp0 GTHE2_CHANNEL_X1Y23 MGTXTXN3_115_W1 PCIE_TX0_N PERn0 GTHE2_CHANNEL_X1Y23 MGTXRXP3_115_Y4 PCIE_RX0_P PETp0 GTHE2_CHANNEL_X1Y23 MGTXRXN3_115_Y3 PCIE_RX0_N PETn0 GTHE2_CHANNEL_X1Y23 MGTREFCLK0P_115_Y8 MGT_BANK_115 MGTREFCLK0N_115_Y7 MGT_BANK_115 MGTREFCLK1P_115_AB8 PCIE_CLK_Q0_N REFCLK- MGT_BANK_115 MGTREFCLK1N_115_AB7 PCIE_CLK_Q0_P REFCLK+ MGT_BANK_115 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 42 For more information refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 5] and 7 Series FPGAs Integrated Block for PCI Express User Guide (PG054) [Ref www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 43: Sfp/Sfp+ Module Connectors

    0.1UF 0.1UF TXS0108E VCCR VCCB SFP1_TX_FAULT_LS SFP1_TX_FAULT SFP1_TX_DISABLE_LS SFP1_TX_DISABLE SFP1_MOD_DETECT_LS SFP1_MOD_DETECT SFP1_RS0_LS SFP1_RS0 SFP1_RS1_LS SFP1_RS1 SFP1_LOS_LS SFP1_LOS TSSOP_20 UG887_C1_15_012113 Figure 1-16: SFP+ Module Connector Circuit (Typical at Four Locations) VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 44 TX_N SFP2_RX_P RD_P SFP2_RX_N RD_N SFP+ Module 3 (P4) SFP3_TX_P TX_P SFP3_TX_N TX_N SFP3_RX_P RD_P SFP3_RX_N RD_N SFP+ Module 4 (P5) SFP4_TX_P TX_P SFP4_TX_N TX_N SFP4_RX_P RD_P SFP4_RX_N RD_N www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 45 MOD_ABS AE39 SFP4_RS0 LVCMOS18 AE40 SFP4_RS1 LVCMOS18 AD40 SFP4_LOS LVCMOS18 AC40 SFP4_TX_DISABLE LVCMOS18 TX_DISABLE Note: The six control/status signals to/from each SFP+ connector are routed through a level shifter. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 46: Usb-To-Uart Bridge

    USB cable is plugged into the USB port on the VC709 board. Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

  • Page 47: I2C Bus

    U14 is at I²C address 0x75 (0b1110101) and the SFP+ modules all have the same address 0x50 (0b1010000). Table 1-17: I C Bus Addresses C Switch C Bus C Address Position PCA9548 0b1110100 USER_CLK_SDL/SCL 0b1011101 FMC1_HPC_IIC_SDA/SCL 0bxxxxx00 NOT USED NOT USED VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 48: Status Leds

    DS14 PWRCTL1_VCC4A_PG GREEN FMC1 HPC power good DS16 VCC12_P_IN GREEN 12V power ON DS17 PWRCTL_PWRGOOD GREEN TI power system power good DS18 LINEAR_POWER_GOOD GREEN DDR3 SODIMMs VTT power good www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 49: User I/O

    R154 R153 R152 R151 R150 R149 R148 R147 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 1/10W 1/10W 1/10W 1/10W 1/10W 1/10W 1/10W 1/10W UG887_c1_17_090612 Figure 1-18: User LEDs VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 50 TL3301EF100QG TL3301EF100QG TL3301EF100QG GPIO_SW_W GPIO_SW_C GPIO_SW_E 4.7K 4.7K 4.7K 1/10W 1/10W 1/10W VCC1V8 VCC1V8 Pushbutton Pushbutton TL3301EF100QG TL3301EF100QG CPU_RESET GPIO_SW_S 4.7K 4.7K 1/10W 1/10W UG887_c1_18_090612 Figure 1-19: User Pushbuttons www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 51 GPIO_LED_7 LVCMOS18 DS9.2 Directional Pushbutton Switches AR40 GPIO_SW_N LVCMOS18 SW3.3 AU38 GPIO_SW_E LVCMOS18 SW4.3 AP40 GPIO_SW_S LVCMOS18 SW5.3 AW40 GPIO_SW_W LVCMOS18 SW7.3 AV39 GPIO_SW_C LVCMOS18 SW6.3 8-Pole DIP Switch VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 52: Switches

    2]for further details on configuring the 7 series FPGAs. Figure 1-21 shows SW9. X-Ref Target - Figure 1-21 VCC1V8 4.7kΩ 0.1 W FPGA_PROG_B UG887_c1_22_090612 Figure 1-21: FPGA_PROG_B Pushbutton SW9 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 53 Figure 1-23 for powering the VC709 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109. For information on ordering this cable, see [Ref 20].

  • Page 54: Vita 57.1 Fmc1 Hpc Connector (Partially Populated)

    The VC709 board FMC1 HPC connector J35 implements a subset of the maximum signal and clock connectivity capabilities: • 80 differential user-defined pairs: • 34 LA pairs (LA00-LA33) • 24 HA pairs (HA00-HA23) • 22 HB pairs (HB00-HB21) www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 55 FMC1_HPC_DP8_M2C_P FMC1_HPC_DP3_M2C_P FMC1_HPC_DP8_M2C_N FMC1_HPC_DP3_M2C_N FMC1_HPC_DP7_M2C_P FMC1_HPC_DP4_M2C_P FMC1_HPC_DP7_M2C_N FMC1_HPC_DP4_M2C_N FMC1_HPC_DP6_M2C_P FMC1_HPC_DP5_M2C_P FMC1_HPC_DP6_M2C_N FMC1_HPC_DP5_M2C_N FMC1_HPC_GBTCLK1_M2C_P FMC1_HPC_DP1_C2M_P FMC1_HPC_GBTCLK1_M2C_N FMC1_HPC_DP1_C2M_N FMC1_HPC_DP9_C2M_P FMC1_HPC_DP2_C2M_P FMC1_HPC_DP9_C2M_N FMC1_HPC_DP2_C2M_N FMC1_HPC_DP8_C2M_P FMC1_HPC_DP3_C2M_P FMC1_HPC_DP8_C2M_N FMC1_HPC_DP3_C2M_N FMC1_HPC_DP7_C2M_P FMC1_HPC_DP4_C2M_P FMC1_HPC_DP7_C2M_N FMC1_HPC_DP4_C2M_N FMC1_HPC_DP6_C2M_P VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 56 U19.14 VCC12_P FMC1_TDI_BUF U19.18 VCC3V3 FMC1_TDO_FPGA_TDI VCC3V3 FMC1_HPC_TMS_BUF U19.17 VCC3V3 VCC3V3 VCC3V3 FMC1_HPC_HA01_CC_P LVCMOS18 FMC1_HPC_PG_M2C LVCMOS18 AN34 FMC1_HPC_HA01_CC_N LVCMOS18 FMC1_HPC_HA00_CC_P LVCMOS18 FMC1_HPC_HA05_P LVCMOS18 FMC1_HPC_HA00_CC_N LVCMOS18 FMC1_HPC_HA05_N LVCMOS18 FMC1_HPC_HA04_P LVCMOS18 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 57 LVCMOS18 FMC1_HPC_LA03_N LVCMOS18 FMC1_HPC_LA02_N LVCMOS18 FMC1_HPC_LA08_P LVCMOS18 FMC1_HPC_LA04_P LVCMOS18 FMC1_HPC_LA08_N LVCMOS18 FMC1_HPC_LA04_N LVCMOS18 FMC1_HPC_LA12_P LVCMOS18 FMC1_HPC_LA07_P LVCMOS18 FMC1_HPC_LA12_N LVCMOS18 FMC1_HPC_LA07_N LVCMOS18 FMC1_HPC_LA16_P LVCMOS18 FMC1_HPC_LA11_P LVCMOS18 FMC1_HPC_LA16_N LVCMOS18 FMC1_HPC_LA11_N LVCMOS18 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 58 LVCMOS18 FMC1_HPC_HA22_P LVCMOS18 FMC1_HPC_HA21_N LVCMOS18 FMC1_HPC_HA22_N LVCMOS18 FMC1_HPC_HA23_P LVCMOS18 FMC1_HPC_HB01_P LVCMOS18 FMC1_HPC_HA23_N LVCMOS18 FMC1_HPC_HB01_N LVCMOS18 FMC1_HPC_HB00_CC_P LVCMOS18 FMC1_HPC_HB07_P LVCMOS18 FMC1_HPC_HB00_CC_N LVCMOS18 FMC1_HPC_HB07_N LVCMOS18 FMC1_HPC_HB06_CC_P LVCMOS18 FMC1_HPC_HB11_P LVCMOS18 FMC1_HPC_HB06_CC_N LVCMOS18 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 59: Power Management

    J5 pin 10 net PMBUS_DATA is level-shifted to 1.8V by Q6 and is connected to U1 bank 15 pin AY39. • J5 pin 8 net PMBUS_ALERT is level-shifted to 1.8V by Q7 and is connected to U1 bank 15 pin AV38. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 60 5.0V at 1.5A Max LMZ12002 U36 Linear Regulator XADC_VCC 1.7V–2V at 300mA REF3012 U35 Switching Regulator VCC3V3 0.75V at 3A Max TPS51200 U23 UG887_c1_24_012113 Figure 1-25: Onboard Power Regulators www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 61 1.80V dual 10A, 0.6V to 3.6V Linear regulators LMZ12002 Fixed linear regulator 2A VCC5V0 5.00V TPS51200DR Tracking regulator, 3A VTTDDR 0.75V ADP123 Fixed linear regulator, 300 mA XADC_VCC 1.80V VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 62: Fmc_Vadj Voltage

    PMBus. The PMBus connector, J5, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the Texas Instruments Xilinx USB website and the associated TI Fusion Digital Power Designer...
  • Page 63 1.53 2.07 Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 64: Xadc Analog-To-Digital Converter

    7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 8] for details on the capabilities of the analog front end. Figure 1-26 shows the XADC block diagram. www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 65 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-27 shows the XADC header connections (Figure 1-2, callout 23). Note: VADJ is fixed at 1.8V on the VC709 board. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 66: Configuration Options

    The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) settings selected through DIP switch SW11. Table 1-26 lists the supported mode switch settings. www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 67 EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit datapath from the linear BPI flash memory at a maximum synchronous read rate of 80 MHz. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 68 FLASH_A[25:0] A[26:1] A[23:16] A[15:0] D[15:0] D[15:0] Bank 14 (VCCO = 1.8V) CE_B FCS_B WAIT RDWR_B (VCC, VCCQ, 1.8V) Oscillator EMCCLK 80 MHz UG887_c1_28_052213 Figure 1-29: VC709 Board Configuration Circuit www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 69: Gpio Dip Switch Sw2

    2 3 4 5 6 7 8 OFF Position = 0 UG887_aA_01_083012 Figure A-1: SW2 Default Settings Table A-1: SW2 Default Switch Settings Position Function Default GPIO_DIP_SW0 GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 GPIO_DIP_SW4 GPIO_DIP_SW5 GPIO_DIP_SW6 GPIO_DIP_SW7 VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 70: Configuration Dip Switch Sw11

    Figure A-2: SW11 Default Settings The default mode setting M[2:0] = 010 selects Master BPI configuration at board power-on. Table A-2: SW11 Default Switch Settings Position Function Default FLASH_A25 FLASH_A24 FPGA_M2 FPGA_M1 FPGA_M0 www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 71: Default Jumper Settings

    TI controller U64 Addr 54 Reset jumper None XADC VCC5V0-to-XADC_VCC5V0 jumper XADC REF3012 U35 VIN select PCIe bus width select header X-Ref Target - Figure A-3 UG887_aA_03_101314 Figure A-3: VC709 Board Jumper Locations VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 72 Appendix A: Default Switch and Jumper Settings www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 73: Appendix B: Vita 57.1 Fmc Connector Pinouts

    HB20_P HB21_N 12P0V HB17_P_CC HB18_N LA32_P DP6_C2M_N HB20_N 3P3V HB17_N_CC LA32_N DP5_C2M_P VADJ VADJ 3P3V DP5_C2M_N VIO_B_M2C VADJ VADJ 3P3V RES0 VIO_B_M2C UG887_aB_01_083012 Figure B-1: FMC1 HPC Connector Pinout VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 74 Appendix B: VITA 57.1 FMC Connector Pinouts www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 75: Vc709 Board Xdc Listing

    Appendix C Master Constraints File Listing The VC709 board master Xilinx design constraints (XDC) file template provides for designs targeting the VC709 board. Net names in the constraints listed in this appendix correlate with net names on the latest VC709 board schematic. Users must identify the appropriate pins and replace the net names listed here with net names in the user RTL.
  • Page 76 PACKAGE_PIN K17 [get_ports DDR3_A_CAS_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CAS_B] set_property PACKAGE_PIN K19 [get_ports DDR3_A_CKE0] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE0] set_property PACKAGE_PIN J18 [get_ports DDR3_A_CKE1] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE1] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 77 IOSTANDARD SSTL15 [get_ports DDR3_A_D22] set_property PACKAGE_PIN G14 [get_ports DDR3_A_D23] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D23] set_property PACKAGE_PIN B14 [get_ports DDR3_A_D24] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D24] set_property PACKAGE_PIN C13 [get_ports DDR3_A_D25] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 78 PACKAGE_PIN D28 [get_ports DDR3_A_D52] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D52] set_property PACKAGE_PIN B31 [get_ports DDR3_A_D53] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D53] set_property PACKAGE_PIN A31 [get_ports DDR3_A_D54] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D54] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 79 IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS4_P] set_property PACKAGE_PIN E25 [get_ports DDR3_A_DQS5_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS5_N] set_property PACKAGE_PIN F25 [get_ports DDR3_A_DQS5_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS5_P] set_property PACKAGE_PIN B29 [get_ports DDR3_A_DQS6_N] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 80 PACKAGE_PIN AM19 [get_ports DDR3_B_A14] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A14] set_property PACKAGE_PIN AL19 [get_ports DDR3_B_A15] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A15] set_property PACKAGE_PIN AR17 [get_ports DDR3_B_BA0] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_BA0] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 81 IOSTANDARD SSTL15 [get_ports DDR3_B_D17] set_property PACKAGE_PIN AW21 [get_ports DDR3_B_D18] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D18] set_property PACKAGE_PIN AV21 [get_ports DDR3_B_D19] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D19] set_property PACKAGE_PIN AU23 [get_ports DDR3_B_D20] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 82 PACKAGE_PIN AR15 [get_ports DDR3_B_D47] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D47] set_property PACKAGE_PIN AL15 [get_ports DDR3_B_D48] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D48] set_property PACKAGE_PIN AJ15 [get_ports DDR3_B_D49] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D49] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 83 IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS2_N] set_property PACKAGE_PIN AT21 [get_ports DDR3_B_DQS2_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS2_P] set_property PACKAGE_PIN BB22 [get_ports DDR3_B_DQS3_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS3_N] set_property PACKAGE_PIN BA22 [get_ports DDR3_B_DQS3_P] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 84 PACKAGE_PIN AH30 [get_ports FLASH_A9] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A9] set_property PACKAGE_PIN AH29 [get_ports FLASH_A10] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A10] set_property PACKAGE_PIN AL30 [get_ports FLASH_A11] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A11] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 85 IOSTANDARD LVCMOS18 [get_ports FLASH_D10] set_property PACKAGE_PIN AK35 [get_ports FLASH_D11] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D11] set_property PACKAGE_PIN AL35 [get_ports FLASH_D12] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D12] set_property PACKAGE_PIN AJ31 [get_ports FLASH_D13] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 86 PACKAGE_PIN G5 [get_ports FMC1_HPC_DP5_M2C_N] set_property PACKAGE_PIN G6 [get_ports FMC1_HPC_DP5_M2C_P] set_property PACKAGE_PIN G1 [get_ports FMC1_HPC_DP6_C2M_N] set_property PACKAGE_PIN G2 [get_ports FMC1_HPC_DP6_C2M_P] set_property PACKAGE_PIN F7 [get_ports FMC1_HPC_DP6_M2C_N] set_property PACKAGE_PIN F8 [get_ports FMC1_HPC_DP6_M2C_P] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 87 IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA08_N] set_property PACKAGE_PIN J36 [get_ports FMC1_HPC_HA08_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA08_P] set_property PACKAGE_PIN D32 [get_ports FMC1_HPC_HA09_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA09_N] set_property PACKAGE_PIN E32 [get_ports FMC1_HPC_HA09_P] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 88 PACKAGE_PIN F36 [get_ports FMC1_HPC_HA22_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA22_P] set_property PACKAGE_PIN A36 [get_ports FMC1_HPC_HA23_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA23_N] set_property PACKAGE_PIN A35 [get_ports FMC1_HPC_HA23_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA23_P] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 89 PACKAGE_PIN P26 [get_ports FMC1_HPC_HB13_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB13_N] set_property PACKAGE_PIN P25 [get_ports FMC1_HPC_HB13_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB13_P] set_property PACKAGE_PIN H21 [get_ports FMC1_HPC_HB14_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB14_N] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 90 IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA05_N] set_property PACKAGE_PIN M41 [get_ports FMC1_HPC_LA05_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA05_P] set_property PACKAGE_PIN J42 [get_ports FMC1_HPC_LA06_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA06_N] set_property PACKAGE_PIN K42 [get_ports FMC1_HPC_LA06_P] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 91 PACKAGE_PIN Y30 [get_ports FMC1_HPC_LA20_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA20_N] set_property PACKAGE_PIN Y29 [get_ports FMC1_HPC_LA20_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA20_P] set_property PACKAGE_PIN N29 [get_ports FMC1_HPC_LA21_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA21_N] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 92 IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW0] set_property PACKAGE_PIN AY33 [get_ports GPIO_DIP_SW1] set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW1] set_property PACKAGE_PIN BA31 [get_ports GPIO_DIP_SW2] set_property IOSTANDARD LVCMOS18 [get_ports GPIO_DIP_SW2] set_property PACKAGE_PIN BA32 [get_ports GPIO_DIP_SW3] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 93 PACKAGE_PIN AB7 [get_ports PCIE_CLK_QO_N] set_property PACKAGE_PIN AB8 [get_ports PCIE_CLK_QO_P] set_property PACKAGE_PIN AV35 [get_ports PCIE_PERST_LS] set_property IOSTANDARD LVCMOS18 [get_ports PCIE_PERST_LS] set_property PACKAGE_PIN Y3 [get_ports PCIE_RX0_N] set_property PACKAGE_PIN Y4 [get_ports PCIE_RX0_P] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 94 PACKAGE_PIN AB41 [get_ports SFP1_TX_DISABLE_LS_B] set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_DISABLE_LS_B] set_property PACKAGE_PIN Y38 [get_ports SFP1_TX_FAULT_LS] set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_FAULT_LS] set_property PACKAGE_PIN AP3 [get_ports SFP1_TX_N] set_property PACKAGE_PIN AP4 [get_ports SFP1_TX_P] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 95 PACKAGE_PIN AC40 [get_ports SFP4_TX_DISABLE_LS_B] set_property IOSTANDARD LVCMOS18 [get_ports SFP4_TX_DISABLE_LS_B] set_property PACKAGE_PIN AE38 [get_ports SFP4_TX_FAULT_LS] set_property IOSTANDARD LVCMOS18 [get_ports SFP4_TX_FAULT_LS] set_property PACKAGE_PIN AL1 [get_ports SFP4_TX_N] set_property PACKAGE_PIN AL2 [get_ports SFP4_TX_P] VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 96 PACKAGE_PIN AN38 [get_ports XADC_VAUX0P_R] set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX0P_R] set_property PACKAGE_PIN AM42 [get_ports XADC_VAUX8N_R] set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX8N_R] set_property PACKAGE_PIN AM41 [get_ports XADC_VAUX8P_R] set_property IOSTANDARD LVCMOS18 [get_ports XADC_VAUX8P_R] www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 97: Appendix D: Board Setup

    ATX power supply 4-pin peripheral connector only through the ATX adapter cable shown in Figure D-1 to J18 on the VC709 board. The Xilinx part number for this cable is 2600304. For information on ordering this cable, see [Ref 20].
  • Page 98 J18 may damage the VC709 board and void the board warranty. Slide the VC709 board power switch SW12 to the ON position. The PC can now be plugged in and powered on. www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 99: Appendix E: Board Specifications

    The VC709 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI Express card. Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C Humidity 10% to 90% non-condensing Operating Voltage +12 V VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...
  • Page 100 Appendix E: Board Specifications www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 101: Appendix F: Additional Resources

    Virtex-7 FPGA VC709 Connectivity Kit Documentation website Virtex-7 VC709 Evaluation Kit Master Answer Record (AR 51901) These Xilinx documents and sites provide supplemental material useful with this guide: 7 Series FPGAs Overview (DS180) 7 Series FPGAs Configuration User Guide (UG470)
  • Page 102 USB to GPIO Interface Adapter) Analog Devices ADP123 20. The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009. Sourcegate only manufactures the latest revision, which is currently A4. To order, contact Aries Ang, aries.ang@sourcegate.net, +65 6483 2878 for price and availability.

  • Page 103: Appendix G: Regulatory And Compliance Information

    EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits and Methods of Measurement This is a Class A product and can cause radio interference. In a domestic environment, the user might be required to take adequate corrective measures. VC709 Evaluation Board www.xilinx.com Send Feedback UG887 (v1.4) December 4, 2014...

  • Page 104: Safety

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. www.xilinx.com VC709 Evaluation Board Send Feedback UG887 (v1.4) December 4, 2014...

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