Xilinx Virtex-4 ML461 User Manual page 51

Termination and Transmission Line Summaries
Table 5-3: DDR2 SDRAM DIMM Terminations
Signal
Data (DQ)
Data Strobe (DQS, DQS)
6 pairs of Clocks (CK, CK),
3 each per DIMM
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE, and others)
Table 5-4: DDR2 SDRAM Components Terminations
Signal
Data (DQ)
Data Strobe (DQS, DQS)
Clock (CK, CK)
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE)
Table 5-5: QDR-II SRAM Terminations
Signal
Write Data (D)
Read Data (Q)
Write Strobe (K, K)
Read Strobe (CQ, CQ)
Clock (CK, CK)
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE, BW)
Virtex-4 ML461 Development Board
UG079 (v1.1) September 5, 2007
FPGA Driver Termination at FPGA
SSTL18_II 50Ω pull-up to 0.9V
DIFF_SSTL18_II No termination
SSTL18_II No termination
SSTL18_II No termination
SSTL18_II No termination
FPGA Driver Termination at FPGA
SSTL18_II 50Ω pull-up to 0.9V
DIFF_SSTL18_II No termination
SSTL18_II No termination
SSTL18_II No termination
SSTL18_II No termination
FPGA Driver Termination at FPGA
HSTL18_I No termination
HSTL18_I_DCI No termination
HSTL18_I No termination
DIFF_HSTL18_II No termination
HSTL18_I No termination
HSTL18_I No termination
HSTL18_I No termination
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Termination at Memory
50Ω pull-up to 0.9V
100Ω differential termination
between pair
100Ω differential termination
between pair
50Ω pull-up to 0.9V after the second
DIMM
50Ω pull-up to 0.9V after the second
DIMM
Termination at Memory
50Ω pull-up to 0.9V
100Ω differential termination
between pair
100Ω differential termination
between pair
50Ω pull-up to 0.9V after the last
component
50Ω pull-up to 0.9V after the last
component
Termination at Memory
50Ω pull-up to 0.9V
No termination
100Ω differential termination between
pair
No termination
100Ω differential termination between
pair
50Ω pull-up to 0.9V after the last
component
50Ω pull-up to 0.9V after the last
component
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