Xilinx Virtex-4 ML461 User Manual page 80

Appendix A: FPGA Pinouts
Table A-4: FPGA #4 Pinout (Continued)
Signal Name
XEN_RX1P
XEN_RX1N
XEN_RX2P
SYNTH_CLK_TO_FPGA4_N
SYNTH_CLK_TO_FPGA4_P
EXT_CLK_TO_FPGA4_N
FPGA4_FPGA1_MII_TX_CLK
FPGA4_FPGA1_MII_TX_DATA0
FPGA4_FPGA1_MII_TX_DATA1
FPGA4_FPGA1_MII_TX_DATA2
FPGA4_FPGA1_MII_TX_DATA3
FPGA4_FPGA1_MII_TX_EN
FPGA4_FPGA1_MII_TX_ERR
FPGA4_FPGA1_MII_TX_SPARE
FPGA4_FPGA2_MII_TX_CLK
FPGA4_FPGA2_MII_TX_DATA0
FPGA4_FPGA2_MII_TX_DATA1
FPGA4_FPGA2_MII_TX_DATA2
FPGA4_FPGA2_MII_TX_DATA3
FPGA4_FPGA2_MII_TX_EN
FPGA4_FPGA2_MII_TX_ERR
FPGA4_FPGA2_MII_TX_SPARE
FPGA4_FPGA3_MII_TX_CLK
FPGA4_FPGA3_MII_TX_DATA0
FPGA4_FPGA3_MII_TX_DATA1
FPGA4_FPGA3_MII_TX_DATA2
FPGA4_FPGA3_MII_TX_DATA3
FPGA4_FPGA3_MII_TX_EN
FPGA4_FPGA3_MII_TX_ERR
80
Pin
Z-DOK+ Connector Interface (cont'd)
AE6 XEN_RX2N
AD6 XEN_RX3P
AF9 XEN_RX3N
FPGA #4 Clock Signals
C14 EXT_CLK_TO_FPGA4_P
C15 DIRECT_CLK_TO_FPGA4_N
B14 DIRECT_CLK_TO_FPGA4_P
FPGA #4 MII Link Interface
F14 FPGA4_FPGA3_MII_TX_SPARE
F11 FPGA1_FPGA4_MII_TX_CLK
F16 FPGA1_FPGA4_MII_TX_DATA0
F15 FPGA1_FPGA4_MII_TX_DATA1
D14 FPGA1_FPGA4_MII_TX_DATA2
F13 FPGA1_FPGA4_MII_TX_DATA3
F12 FPGA1_FPGA4_MII_TX_EN
D13 FPGA1_FPGA4_MII_TX_ERR
AA14 FPGA1_FPGA4_MII_TX_SPARE
AC11 FPGA2_FPGA4_MII_TX_CLK
AA16 FPGA2_FPGA4_MII_TX_DATA0
AA15 FPGA2_FPGA4_MII_TX_DATA1
AB13 FPGA2_FPGA4_MII_TX_DATA2
AB14 FPGA2_FPGA4_MII_TX_DATA3
AC12 FPGA2_FPGA4_MII_TX_EN
AA13 FPGA2_FPGA4_MII_TX_ERR
AE14 FPGA2_FPGA4_MII_TX_SPARE
AD10 FPGA3_FPGA4_MII_TX_CLK
AD17 FPGA3_FPGA4_MII_TX_DATA0
AD16 FPGA3_FPGA4_MII_TX_DATA1
AD12 FPGA3_FPGA4_MII_TX_DATA2
AE13 FPGA3_FPGA4_MII_TX_DATA3
AE10 FPGA3_FPGA4_MII_TX_EN
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
AE9
AD8
AC8
B15
A15
A16
AD11
D15
D11
D16
C16
E13
E14
C11
D12
AC14
AA11
AC16
AC15
AC13
AD14
AA12
AD13
AF12
AB10
AB17
AC17
AF11
AE12