Xilinx Virtex-4 ML461 User Manual page 94

Appendix B: LCD Interface
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Because of these default settings, the following display controller connections are not used:
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When RESETB is Low, the display controller is initialized as indicated in
Table B-4: Display Controller Initialization (RESETB is Low)
When RESETB is High, the display must be initialized. The first steps to be taken to
guarantee correct operation of the display and the controller are:
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Internal voltage divider resistors
Temperature coefficient is set to -0.05%/°C
Normal power mode is set
The voltage follower and voltage regulator are set to:
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Five times boost mode
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The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.
DISP: Turns into an output when Master mode is selected
FRS: Static driver segment output
M: Used in Master/Slave display configurations
CL: Clock pin used in Master/Slave display configurations
Parameter
Display
Entire display
ADC select
Reverse display
Power control
LCD bias
Read-modify-write
SHL select
Static indicator mode
Static indicator register
Display start
Column address
Page address
Regulator select
Reference voltage
Reference voltage register
Configure the ADC bit. This bit determines the scanning direction of the segments.
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When the RESETB signal is active, ADC is reset to 0, meaning that the segments
are scanned from SEG1 up to SEG132.
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When ADC is set to 1, the segments are scanned in opposite direction.
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Initial Value
OFF
OFF
OFF
OFF
0,0,0 (VC, VR, VF)
1/7
OFF
OFF
OFF
0,0 (S1, S0)
0 (First line)
0
0
0,0,0 (R2, R1, R0)
OFF
1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)
Virtex-4 ML461 Development Board User Guide
Table B-4.
UG079 (v1.1) September 5, 2007
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