Xilinx Virtex-4 ML461 User Manual page 72

Appendix A: FPGA Pinouts
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
QDR2_Q_BY2_B8
QDR2_Q_BY3_B0
QDR2_Q_BY3_B1
QDR2_Q_BY3_B2
QDR2_Q_BY3_B3
QDR2_Q_BY3_B4
QDR2_Q_BY3_B5
QDR2_Q_BY3_B6
QDR2_Q_BY3_B7
QDR2_Q_BY3_B8
QDR2_Q_BY4_B0
QDR2_Q_BY4_B1
QDR2_Q_BY4_B2
QDR2_Q_BY4_B3
QDR2_Q_BY4_B4
QDR2_Q_BY4_B5
QDR2_Q_BY4_B6
QDR2_Q_BY4_B7
QDR2_Q_BY4_B8
QDR2_Q_BY5_B0
QDR2_Q_BY5_B1
QDR2_Q_BY5_B2
QDR2_Q_BY5_B3
QDR2_Q_BY5_B4
QDR2_Q_BY5_B5
QDR2_Q_BY5_B6
QDR2_Q_BY5_B7
QDR2_Q_BY5_B8
QDR2_Q_BY6_B0
QDR2_Q_BY6_B1
QDR2_Q_BY6_B2
72
Pin
QDR II Memory Interface (cont'd)
U21 QDR2_Q_BY6_B3
AB25 QDR2_Q_BY6_B4
AA24 QDR2_Q_BY6_B5
Y24 QDR2_Q_BY6_B6
AC25 QDR2_Q_BY6_B7
AC26 QDR2_Q_BY6_B8
AB26 QDR2_Q_BY7_B0
AA26 QDR2_Q_BY7_B1
AD25 QDR2_Q_BY7_B2
AD26 QDR2_Q_BY7_B3
K2 QDR2_Q_BY7_B4
L4 QDR2_Q_BY7_B5
L3 QDR2_Q_BY7_B6
M8 QDR2_Q_BY7_B7
L8 QDR2_Q_BY7_B8
L1 QDR2_R_N
K1 QDR2_READ_VALID_FAST_LOOPBACK
M2 QDR2_READ_VALID_FAST_LOOPBACK
M1 QDR2_READ_VALID_LOOPBACK
N7 QDR2_READ_VALID_LOOPBACK_BANK7
M7 QDR2_READ_VALID_LOOPBACK_BANK7
P5 QDR2_READ_VALID_LOOPBACK
P4 QDR2_READ_VALID_SLOW_LOOPBACK
P8 QDR2_READ_VALID_SLOW_LOOPBACK
N8 QDR2_SA0
R4 QDR2_SA1
P7 QDR2_SA2
P6 QDR2_SA3
R8 QDR2_SA4
R7 QDR2_SA5
T4 QDR2_SA6
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
T3
T7
T6
U3
V4
U4
AA3
Y4
Y3
Y6
Y5
AB1
AA1
AC4
AB4
AF5
AD19
AB21
AE4
V20
W20
AF4
Y17
AA20
AD4
AC6
AB6
AF8
AF7
AA8
Y8