Xilinx Virtex-4 ML461 User Manual page 52

R
Table 5-6: FCRAM-II SDRAM Terminations
Signal
Data (DQ)
Write Strobe (DS)
Read Strobe (QS)
Clock (CK, CK)
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE)
Table 5-7: RLDRAM-II SDRAM Terminations
Signal
Data (DQ)
Write Strobe (DK, DK)
Read Strobe (QK, QK)
Clock (CK, CK)
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE)
IBIS Simulations
Signal Integrity (SI) simulations were performed during the Virtex-4 ML461 Development
Board layout. The simulations utilized a combination of preliminary Virtex-4 device IBIS
and HSPICE models, as well as memory models available from memory vendors at that
time.
52
FPGA Driver Termination at FPGA
SSTL18_II 50Ω pull-up to 0.9V
SSTL18_I No termination
SSTL18_I 50Ω pull-up to 0.9V
SSTL18_II No termination
SSTL18_II No termination
SSTL18_II No termination
FPGA Driver Termination at FPGA
HSTL18_II 50Ω pull-up to 0.9V
DIFF_HSTL18_II No termination
HSTL18_II No termination
HSTL18_II No termination
HSTL18_II No termination
HSTL18_II No termination
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Termination at Memory
50Ω pull-up to 0.9V
50Ω pull-up to 0.9V
No termination
100Ω differential termination between
pair
50Ω pull-up to 0.9V after the last
component
50Ω pull-up to 0.9V after the last
component
Termination at Memory
50Ω pull-up to 0.9V
100Ω differential termination
between pair
No termination
100Ω differential termination
between pair
50Ω pull-up to 0.9V after the last
component
50Ω pull-up to 0.9V after the last
component
Virtex-4 ML461 Development Board
UG079 (v1.1) September 5, 2007