Virtex-4 Ml461 Memory Interfaces Development Board - Xilinx Virtex-4 ML461 User Manual

Chapter 1: Introduction

Virtex-4 ML461 Memory Interfaces Development Board

A high-level functional block diagram of the Virtex-4 ML461 Memory Interfaces
Development Board is shown in
SSTL2
FPGA #1
LX25/
FF668
Figure 1-1: Virtex-4 ML461 Development Board Block Diagram
The Virtex-4 ML461 Development Board includes the following major functional blocks:
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8
SSTL18
FPGA #2
LX25/
FF668
Four XC4VLX25-FF668 FPGAs (see DS112: Virtex-4 Family Overview)
DDR1 DIMM memory: Two PC-3200 DIMM sockets for up to 64M x 144 bits (see
XAPP709)
DDR400 components: 16M x 28 bits at 200 MHz clock speed
DDR2 DIMM memory: Two PC2-4300 DIMM sockets for up to 64M x 144 bits (see
XAPP702 and XAPP721)
DDR2-533 components: 8M x 28 bits at 267 MHz clock speed
QDR II memory: 2M x 72 bits at up to 300 MHz clock speed (see XAPP703)
RLDRAM II memory: 16M x 36 bits at up to 400 MHz clock speed (see XAPP710)
One DB9-M RS232 port
One 64 x 128 pixel Liquid Crystal Display (LCD)
A System ACE™ CompactFlash (CF) Configuration Controller that allows storing
and downloading of up to eight FPGA configuration image files
On-board power regulators with ±5% output margin test capabilities
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Figure 1-1.
External Interfaces:
System ACE Controller,
ML410 Z-DOK+, LCD
HSTL/SSTL18
FPGA #3
LX25/
FF668
Virtex-4 ML461 Development Board User Guide
HSTL
FPGA #4
LX25/
FF668
UG079_c1_02_072905
UG079 (v1.1) September 5, 2007
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