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Virtex-4 ML461
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Xilinx Virtex-4 ML461 User Manual page 63
Memory interfaces
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Table A-1: FPGA #1 Pinout (Continued)
Signal Name
FPGA1_TEST_HDR_B4
FPGA1_TEST_HDR_B5
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
A10
FPGA1_TEST_HDR_B6
B10
FPGA1_TEST_HDR_B7
www.xilinx.com
FPGA #1 Pinout
Signal Name
Pin
B17
A17
63
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Section 2
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Table of Contents
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