Xilinx Virtex-4 ML461 User Manual page 69

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Table A-2: FPGA #2 Pinout (Continued)
Signal Name
DDR2_DQ_BY3_B3
DDR2_DQ_BY3_B4
DDR2_DQ_BY3_B5
DDR2_DQ_BY3_B6
DDR2_DQ_BY3_B7
DDR2_ODT
DDR2_CK0_N
DDR2_CK0_P
DDR2_CK1_N
DDR2_CK1_P
DDR2_CK2_N
DDR2_CK2_P
DDR2_CK3_N
DDR2_CK3_P
FPGA2_FPGA4_MII_TX_CLK
FPGA2_FPGA4_MII_TX_DATA_B0
FPGA2_FPGA4_MII_TX_DATA_B1
FPGA2_FPGA4_MII_TX_DATA_B2
FPGA2_FPGA4_MII_TX_DATA_B3
FPGA2_FPGA4_MII_TX_EN
FPGA2_FPGA4_MII_TX_ERR
FPGA2_FPGA4_MII_TX_SPARE
FPGA_CNFG_M0
FPGA_CNFG_M1
FPGA_CNFG_M2
FPGA_DIN
FPGA_DONE
FPGA_INIT
FPGA2_TEST_HDR_BY0_B0
FPGA2_TEST_HDR_BY0_B1
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
DDR2 Component Memory Interface (cont'd)
U4
T8
U7
U6
U5
D14
FPGA #2 Clock Signals
AB14
AA14
AC11
AC12
AA15
AA16
AD14
AC14
FPGA #2 MII Link Interface
AE14
AD10
AD17
AD16
AD12
AE13
AE10
AD11
FPGA #2 Configuration Signals
W15
Y15
W14
G12
H14
G15
FPGA #2 Test Header Signals
A12
A11
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Signal Name
DDR2_RAS_N
DDR2_READ_VALID_LOOPBACK
DDR2_READ_VALID_LOOPBACK
DDR2_READ_VALID_LOOPBACK_BANK
9
DDR2_READ_VALID_LOOPBACK_BANK
9
DDR2_WE_N
DDR2_CKE
DIRECT_CLK_TO_FPGA2_N
DIRECT_CLK_TO_FPGA2_P
EXT_CLK_TO_FPGA2_N
EXT_CLK_TO_FPGA2_P
SYNTH_CLK_TO_FPGA2_N
SYNTH_CLK_TO_FPGA2_P
FPGA4_FPGA2_MII_TX_CLK
FPGA4_FPGA2_MII_TX_DATA
FPGA4_FPGA2_MII_TX_DATA
FPGA4_FPGA2_MII_TX_DATA
FPGA4_FPGA2_MII_TX_DATA
FPGA4_FPGA2_MII_TX_EN
FPGA4_FPGA2_MII_TX_ERR
FPGA4_FPGA2_MII_TX_SPARE
FPGA_PROGB
FPGA_TCK
FPGA_TDO
FPGA_TMS
FPGA_VBATT
SYS_RESET_IN_N
FPGA2_TEST_HDR_BY0_B2
FPGA #2 Pinout
Pin
AA12
D8
F10
J21
L26
AC15
AC16
A15
A16
B14
B15
C14
C15
AF12
AB10
AB17
AC17
AF11
AE12
AC10
AF10
H15
W12
Y13
Y11
Y16
K1
B13
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