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Chapter 3: Hardware Description
Characterization
The memory interfaces implemented on the ML461 board have been characterized across
voltage and temperature using various Virtex-4 devices. This section describes the setup
for performing such characterization on the ML461 board. For actual characterization data
obtained with the reference designs implemented on the ML461, please refer to
www.xilinx.com/memory.
Voltage Regulators
Twelve power planes are used on the ML461 Development Board to provide various on-
board voltage sources.
•
•
•
The TI PTH05010-WAS power module provides two input pins to control the voltage
output level. The output can be margined up to +5% of the nominal value by driving pin 10
to GND or digital Low. Similarly, the output can be margined down to -5% of the nominal
value by driving pin 9 Low. There are two ways to apply these digital controls to these
voltage margin input pins:
1.
To control the voltage levels using FPGA #4, make sure there are no jumpers connecting
the header pins listed in
used to control the voltage margining for all the power regulators.
Table 3-12: FPGA #4 Signals for Voltage Margining
30
Connector J9 or a pair of banana jacks (J7 and J8) provides the main +5.0V voltage to
the board.
This +5.0V voltage source is supplied as input to six on-board regulator modules
PTH05010-WAS) to generate the +1.2V, +2.5V, +1.8V for SSTL18, +1.8V for HSTL18,
+2.6V for SSTL2, and +3.3V voltages for the digital section of the board. The HSTL18
power plane can be changed to HSTL power plane for supplying +1.5V by adjusting
the VO_ADJ input of VR3 power regulator module. The value of R1565 then must be
changed from 5.49 KΩ to 8.87 KΩ .
Additional three bulk voltage regulators
termination (V
) and reference (V
TT
HSTL power levels. By design, these voltage levels are half of the input reference
voltage from the corresponding V
The FPGA drives the VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals,
where xxxx indicates one of the six power planes: SSTL2, HSTL, SSTL18, VCC1V2,
VCC2V5, and 3V3.
Table
Power Plane
VCC1V2
SSTL18
SSTL2
HSTL
www.xilinx.com
(Fairchild
) voltages each for the SSTL2, SSTL18, and
REF
planes.
DD
3-12.
Table 3-12
illustrates the signals from FPGA #4 that are
Signal Name
VMARGIN_UP_VCC1V2_N
VMARGIN_DN_VCC1V2_N
VMARGIN_UP_SSTL18_N
VMARGIN_DN_SSTL18_N
VMARGIN_UP_SSTL2_N
VMARGIN_DN_SSTL2_N
VMARGIN_UP_HSTL_N
VMARGIN_DN_HSTL_N
Virtex-4 ML461 Development Board User Guide
ML6554CU) are used to generate
Pin
N21
N20
P25
P24
P23
P22
R26
R25
UG079 (v1.1) September 5, 2007
R
(TI
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