Usb J6 Mini-B Receptacle Pin Assignments And Signal Definitions; Fpga To Uart Connections - Xilinx KC705 User Manual

connector J6). The CP2103GM is powered by the USB 5V provided by the host PC when the
USB cable is plugged into the USB port on the KC705 board.
Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send
(RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer.
These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to
communications application software (for example, Tera Term or HyperTerm) that runs on
the host computer. The VCP device drivers must be installed on the host PC prior to
establishing communications with the KC705 board.
Table 1-19 shows the USB signal definitions at J6.
Table 1-19: USB J6 Mini-B Receptacle Pin Assignments and Signal Definitions
USB Receptacle Receptacle Pin
Pins (J6) Name
1 VBUS
2 D_N
3 D_P
4 GND
Table 1-20 shows the USB connections between the FPGA and the UART.
Table 1-20: FPGA to UART Connections
FPGA U1
Pin Function
L27 RTS
K23 CTS
K24 TX
M19 RX
For more information about the CP2103GM and to download the VCP drivers see
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Schematic Net
Name
USB_VBUS +5V from host system
- U12 CP2103 power
USB_D_N Bidirectional
differential serial data
(N-side)
USB_D_P Bidirectional
differential serial data
(P-side)
USB_GND Signal ground
I/O
Direction
Standard
Output LVCMOS25
Input LVCMOS25
Output LVCMOS25
Input LVCMOS25
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Chapter 1: KC705 Evaluation Board Features
U12 Pin
Description
(CP2103GM)
CP2103 Device U12
Schematic
Net Name
Pin
USB_CTS 22
USB_RTS 23
USB_RX 24
USB_TX 25
U12 Pin Name
(CP2103GM)
7, 8 REGIN, VBUS
4 D-
3 D+
2, 29 GND, GND
Function Direction
CTS Input
RTS Output
RXD Input
TXD Output
[Ref 7].
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