Xilinx Virtex-4 ML461 User Manual page 82

Appendix A: FPGA Pinouts
Table A-4: FPGA #4 Pinout (Continued)
Signal Name
LCD_E
LCD_BL_ON
RS232_CTS
RS232_RTS
VMARGIN_UP_VCC1V2_N
VMARGIN_DN_VCC1V2_N
VMARGIN_UP_SSTL18_N
VMARGIN_DN_SSTL18_N
VMARGIN_UP_SSTL2_N
VMARGIN_DN_SSTL2_N
VMARGIN_UP_HSTL_N
VMARGIN_DN_HSTL_N
VMARGIN_UP_VCC2V5_N
VMARGIN_DN_VCC2V5_N
LOOP_FILTER_UP
LOOP_FILTER_DOWN
VMARGIN_UP_3V3_N
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Pin
LCD Signals (cont'd)
AF24 LCD_CSB
AE24 LCD_RSTB
RS-232 Signals
AC23 RS232_TX
AC24 RS232_RX
Voltage Margin Control Signals
N21 VMARGIN_DN_3V3_N
N20 I2C_CLK
P25 I2C_DATA
P24 CPLD_DGATE_EN
P23 CPLD_GSR
P22 ENABLE0
R26 ENABLE1
R25 ENABLE2
P20 SI_SEL1
P19 MODE"
R24 SEL0
R23 LOAD
T23 SCLK
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
AD20
AD20
AB20
AC20
R20
T26
U26
U23
V23
U22
U21
T21
T20
U20
T19
V26
V25