Xilinx Virtex-4 ML461 User Manual page 90

Appendix B: LCD Interface
Table B-3: KS0713 Pin Connections
Connector J1 Connector J2
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
1 1
2 2
LCD Control Pins
90
PCB
Connected to
Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDD
VDD
VDD
VDD
VDD
VSS
VDD
VSS
VDD
OPEN
OPEN
OPEN
www.xilinx.com
Signal
Description
Name
CS1B Chip enable is active-LOW
RESETB Initialize the LCD
RS Register select
RW_WR Read/Write
E_RD Enable/Read
DB0 8-bit bidirectional data bus.
In serial mode, DB0-DB5 are high
DB1
impedance, DB6 is the serial clock
DB2
input, and DB7 is the serial data
input.
DB3
DB4
DB5
DB6
DB7
MI Processor mode select
PS Parallel or Serial
VSS Ground
VDD Power Supply
CS2 Active-High chip enable
DUTY0 LCD driver duty ratio. Set to 1/65.
DUTY1
MS Master / Slave operation. Set to
Master.
Built-in oscillator enable
CLS
TEMPS Set to -0.05%/°C
INTRS Internal resistors used
HPM Normal mode set
BSTS Voltage converter input is VDD
(2.4<VDD<3.6)
Only used in Master/Slave
DISP
CL Display clock input
M Only used in Master/Slave
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R