Z-Dok+ Port; Test Headers - Xilinx Virtex-4 ML461 User Manual

R
A high-level block diagram of the RS-232 interface is shown in
The RS-232 DB9-F to DB9-F cable included in the kit mates with the P30 connector.

Z-DOK+ Port

For an external processor interface, a pair of Z-DOK+ connectors (Tyco 137555-1) are
provided (at locations PM1 and PM2). Through these connectors, the Virtex-4 ML461
Development Board can plug into an MLx10-series motherboard developed by the Xilinx
APD Systems Engineering Group (SEG).

Test Headers

All four FPGAs have two 16-pin (2X8, 100-mil spacing) headers each, connected to test
header signals on Banks 3 and 4, that is, a total of eight connectors (P1, P2, P3, P4, P21, P27,
P54, and P57).
1.
2.
To provide 16 additional test header signals to access the FPGA ports. The current
implementation of the Rev B1 board provides access to these 16 test headers signals
(FPGAx_TEST_HDR_BY[3:2]_B[7:0]) through connectors P27, P21, P54, and P57 for FPGA
#1, #2, #3, and #4, respectively.
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
U33
TX
RX
Virtex-4
FPGA
#4
RTS
CTS
Figure 3-8: RS-232 Interface Block Diagram
Bank 3 Headers: The 16-pin header connected to Bank 3 signals is exclusively
dedicated for the test signals. Based on the number of spare signals available on
Bank 3, up to eight test signals are accessible at this connector. FPGA #1, FPGA #3, and
FPGA #4 have eight test signals (FPGAx_TEST_HDR_BY0_B[7:0]) on connectors P2,
P3, and P4, respectively. FPGA #2 has only three test signals
(FPGA2_TEST_HDR_BY0_B[2:0]) accessible via connector P1.
Bank 4 Headers: The 16 test signals connected to Bank 4 on each FPGA serve dual
purposes:
♦
To provide connectivity between FPGA #4 and the other three FPGAs via
unidirectional 8-bit MII buses (Tx and Rx). The eight bits are Data[0:3], Clock,
Enable, Error, and Spare. The Rev B1 board does not implement this connectivity.
It can be implemented by populating the corresponding 0Ω resistors. See pages 6,
30, 53, and 70 of ML461 Rev B1 schematics for details.
www.xilinx.com
U25
T1IN T1OUT
R1OUT R1IN
MAX3316
T2IN T2OUT
R2OUT R2IN
External Interfaces
Figure 3-8.
P30
3
2
DB9-M
7
8
ug079_08_072905
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