Xilinx Virtex-4 ML461 User Manual page 22

Chapter 3: Hardware Description
Table 3-5
list of FPGA #2 signals and their pin locations, refer to
Table 3-5: DDR2 Component Signal Summary
Board Signal Name(s)
DDR2_A[12:0]
DDR2_CK[3:0]_[P,N]
DDR2_ODT,
DDR2_[RAS,CAS,WE]_N,DDR2_CKE,
DDR2_BA[1:0], DDR2_CS[3:0]_N,
DDR2_DM_BY[3:0]
DDR2_DQ_BY0_B[3:0],
DDR2_DQS_BY0_L_[P,N]
DDR2_DQ_BY1_B[7:0],
DDR2_DQS_BY1_[P,N]
DDR2_DQ_BY2_B[7:0],
DDR2_DQS_BY2_[P,N]
DDR2_DQ_BY3_B[7:0],
DDR2_DQS_BY3_[P,N]
Notes:
1. DDR2_CKE and DDR2_ODT signals are connected to a 4.7K pull-down resistor.
A copy of XAPP702: "DDR-2 Controller Using Virtex-4 Devices" and its corresponding
reference design RTL code are included on the CD shipped with the ML461 Tool Kit.
22
describes all signals associated with DDR2 Component memories. For a complete
Bits
13 DDR2 Component Address
8 DDR2 Component Differential Clock
14 DDR2 Component Control Signals
6 DDR2 Data and Strobe: Byte 0
10 DDR2 Data and Strobe: Byte 1
10 DDR2 Data and Strobe: Byte 2
10 DDR2 Data and Strobe: Byte 3
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Appendix A, "FPGA Pinouts."
Description
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Bank Schematic
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