Ddr400 Memory - Xilinx Virtex-4 ML461 User Manual

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DDR400 Memory

The FPGA #1 device on the Virtex-4 ML461 Development Board is connected to DDR1
memories. The DDR1 memory interface includes:
•
•
For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of
the FPGA #1 device.
component interface signals among the different banks of the FPGA #1 device.
Table 3-2
a bus or a group of signals, a shorthand method is used to describe these signals and
follows these rules:
1.
2.
3.
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
a 144-bit-wide DIMM connection to two 184-pin DDR1 DIMM sockets
a 28-bit-wide datapath to four DDR400 memory discrete components
Figure 3-4
BANK 6 (64)
DIMM Bytes:
2, 3, 10, 11
Component Bytes:
0
BANK 10 (64)
DIMM Addr/Cntl
Component Bytes:
3
BANK 8 (64)
DIMM Bytes:
4, 5, 12, 13
Note: Banks 1 & 2 do not have DCI capability due to lack of VRP/VRN.
Figure 3-4: FPGA #1 Banks for DDR1 (SSTL2) Interfaces (Top View)
describes all the signals associated with DDR1 DIMM component memories. For
All entities with a pair of square brackets represent a different signal.
For example, DDR1_[RAS,CAS,WE]_N represents three signals: DDR1_RAS_N,
DDR1_CAS_N, and DDR1_WE_N.
All numbers are represented as a range, for example, n:m, expands into (n-m+1)
unique signals.
For example, DDR1_A[12:0] represents 13 separate signals: DDR1_A12, DDR1_A11,
...., DDR1_A0.
Other items are listed within brackets separated by commas.
www.xilinx.com
summarizes the distribution of DDR1 DIMM and discrete
BANK 1 (16)
Component Address
BANK 3 (16)
Inter-FPGA SERDES Links
BANK 0
(Configuration)
BANK 4 (16)
Global Clock Inputs
BANK 2 (16)
Component Control/Clocks
Memory Interfaces
BANK 5 (64)
DIMM Bytes:
0, 1, 8, 9
BANK 9 (64)
DIMM Bytes:
CB0_7, CB8_15
Component Bytes:
1,2
BANK 7 (64)
DIMM Bytes:
6, 7, 14, 15
UG079_c3_04_072905
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