Xilinx Virtex-4 ML461 User Manual page 81

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Table A-4: FPGA #4 Pinout (Continued)
Signal Name
FPGA3_FPGA4_MII_TX_ERR
FPGA_CNFG_M0
FPGA_CNFG_M1
FPGA_CNFG_M2
FPGA_DIN
FPGA_DONE
FPGA_INIT
FPGA4_TEST_HDR_B0
FPGA4_TEST_HDR_B1
FPGA4_TEST_HDR_B2
FPGA4_TEST_HDR_B3
SYSACE_CTRL0
SYSACE_CTRL1
SYSACE_CTRL2
SYSACE_CTRL3
SYSACE_CTRL4
SYSACE_MPA0
SYSACE_MPA1
SYSACE_MPA2
SYSACE_MPA3
SYSACE_MPA4
SYSACE_MPA5
LCD_DB0
LCD_DB1
LCD_DB2
LCD_DB3
LCD_DB4
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
FPGA #4 MII Link Interface (cont'd)
AC10 FPGA3_FPGA4_MII_TX_SPARE
FPGA #4 Configuration Signals
W15 FPGA_PROGB
Y15 FPGA_TCK
W14 FPGA_TDO
G12 FPGA_TMS
H14 FPGA_VBATT
G15 SYS_RESET_IN_N
FPGA #4 Test Header Signals
A12 FPGA4_TEST_HDR_B4
A11 FPGA4_TEST_HDR_B5
B13 FPGA4_TEST_HDR_B6
B12 FPGA4_TEST_HDR_B7
System ACE Interface
W21 SYSACE_MPA6
W26 SYSACE_MPD0
W25 SYSACE_MPD1
V22 SYSACE_MPD2
V21 SYSACE_MPD3
Y26 SYSACE_MPD4
Y25 SYSACE_MPD5
V20 SYSACE_MPD6
W20 SYSACE_MPD7
W24 SYSACE_CLK
W23 FPGA_DONE
LCD Signals
AF19 LCD_DB5
AF20 LCD_DB6
Y19 LCD_DB7
W19 LCD_RS
AF23 LCD_R_WB
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FPGA #4 Pinout
Signal Name Pin
AF10
H15
W12
Y13
Y11
Y16
N3
A10
B10
B17
A17
W22
AB26
AC25
Y24
AA24
AB21
AC21
AB25
AB24
AC26
AA26
AE23
Y20
Y21
AA18
Y18
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