Direct Clocking Data Capture Method - Xilinx Virtex-4 ML461 User Manual

Chapter 3: Hardware Description

Direct Clocking Data Capture Method

The read data capture technique for all five memories (DDR1, DDR2, QDR II, and
RLDRAM II) is labeled as Direct Clocking method. Refer to XAPP701: "Memory Interfaces
Data Capture Using Direct Clocking Technique" for a detailed description.
shows a basic block diagram for all external memory interfaces on the Virtex-4 ML461
Development Board.
Memory Interfaces Board
System
DCM Clocks
Clock
DCM
User
Interface
(Testbench)
The memory controller in the respective FPGA sits in between the physical layer to the
external memory devices and the user interface. Refer to the respective application notes of
reference designs for each memory interface to understand the details of the memory
controller implementations.
16
Memory
Controller
Rd/Wr Addr State
Machine
Write Data
Read Data
Figure 3-3: Basic Memory Controller Block Diagram
www.xilinx.com
FPGA
Memory
Clock
Address and Controls
DCM Clocks
Data Bus
Ctrl
Datapath
Clock/Strobe
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Figure 3-3
CLKs
External
Memory
Device
UG079_c3_03_082807
R