Xilinx Virtex-4 ML461 User Manual page 74

Appendix A: FPGA Pinouts
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
FCR2_DQ_BY2_B8
FCR2_DQ_BY3_B0
FCR2_DQ_BY3_B1
FCR2_DQ_BY3_B2
FCR2_DQ_BY3_B3
FCR2_DQ_BY3_B4
FCR2_DQ_BY3_B5
FCR2_DQ_BY3_B6
FCR2_DQ_BY3_B7
FCR2_DQ_BY3_B8
SYNTH_CLK_TO_FPGA3_N
SYNTH_CLK_TO_FPGA3_P
DIRECT_CLK_TO_FPGA3_N
FPGA4_FPGA3_MII_TX_CLK
FPGA4_FPGA3_MII_TX_DATA_B0
FPGA4_FPGA3_MII_TX_DATA_B1
FPGA4_FPGA3_MII_TX_DATA_B2
FPGA4_FPGA3_MII_TX_DATA_B3
FPGA4_FPGA3_MII_TX_EN
FPGA4_FPGA3_MII_TX_ERR
FPGA4_FPGA3_MII_TX_SPARE
FPGA_CCLK
FPGA_CNFG_M0
FPGA_CNFG_M1
FPGA_CNFG_M2
FPGA_DIN
FPGA_DONE
FPGA_INIT
74
Pin
FCRAM II Memory Interface (cont'd)
C21 FCR2_DS_BY0_1
G18 FCR2_DS_BY2_3
G17 FCR2_FN
B24 FCR2_PD_N
B23 FCR2_QS_BY0_1
F18 FCR2_QS_BY2_3
E18 FCR2_READ_VALID_LOOPBACK
A20 FCR2_READ_VALID_LOOPBACK_BANK5
A19 FCR2_READ_VALID_LOOPBACK_BANK5
D22
FPGA #3 Clock Signals
C14 DIRECT_CLK_TO_FPGA3_P
C15 EXT_CLK_TO_FPGA3_N
A15 EXT_CLK_TO_FPGA3_P
FPGA #3 MII Link Interface
AF12 FPGA3_FPGA4_MII_TX_CLK
AB10 FPGA3_FPGA4_MII_TX_DATA_B0
AB17 FPGA3_FPGA4_MII_TX_DATA_B1
AC17 FPGA3_FPGA4_MII_TX_DATA_B2
AF11 FPGA3_FPGA4_MII_TX_DATA_B3
AE12 FPGA3_FPGA4_MII_TX_EN
AC10 FPGA3_FPGA4_MII_TX_ERR
AF10 FPGA3_FPGA4_MII_TX_SPARE
FPGA #3 Configuration Signals
G14 FPGA_PROGB
W15 FPGA_TCK
Y15 FPGA_TDO
W14 FPGA_TMS
G12 FPGA_VBATT
H14 SYS_RESET_IN_N
G15
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
E9
C19
H24
H23
B6
A24
C4
H25
H26
A16
B14
B15
AE14
AD10
AD17
AD16
AD12
AE13
AE10
AD11
H15
W12
Y13
Y11
Y16
K3