Xilinx Virtex-4 ML461 User Manual page 46

Chapter 4: Electrical Requirements
Table 4-6: Measured Power Consumption (Continued)
Configuration Image
DDR2 Registered DIMM
72-bit Design using
SSTL18_II_DCI for DQ and
ODT on DDR2 Memory
DDR2 Registered DIMM
144-bit Design using
SSTL18_II_DCI for DQ
QDR2 72-bit Design
RLDRAM II 36-bit Design
The ML461 Memory Board contains four Virtex-4 VC4VLX25 FF668 Engineering Sample
(ES) parts. A known errata exists for these ES parts causing excessive V
consumed at power-up. This is evident when comparing the power being consumed at
power-up to the power being consumed where all the FPGAs are loaded with a blank
design. To learn more about this errata, visit www.xilinx.com.
Table 4-7
tested on the ML461. This data was extrapolated from the measured current data listed in
Table
Table 4-7: Estimated Current Usage
Configuration Image
DDR1 Registered DIMM 144-bit Design
DDR2 Registered DIMM 144-bit Design
using SSTL18_II_DCI for DQ and ODT
on DDR2 Memory
RLDRAM II 72-bit Design
(not implemented on the ML461 board)
46
Freq
(MHz)
1.2V 2.5V
267 1.32 3.25
267 2.04 4.50
300 1.32 3.00
267 1.08 2.75
and Table 4-8 show estimated values for current and power consumption not
4-5.
Freq
(MHz)
1.2V
200 1400
267 1700
267 1400
www.xilinx.com
Power Consumption (Watts)
SSTL18 SSTL2
3.3V
1.8V 2.6V
1.98 8.28 2.86
1.98 13.14 2.86
2.31 3.06 2.86
1.98 1.98 2.86
Power Plane Current Usage (mA)
SSTL18
2.5V 3.3V
1700 800
1800 600
1100 600
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
HSTL
TOTAL Design
1.8V
0.18 17.87 11.22
0.18 24.70 18.05
1.80 14.35 7.70
1.26 11.91 5.26
power to be
CCAUX
SSTL2 HSTL
1.8V 2.6V 1.8V
900 5100 100
8300 1100 100
1100 1100 1300
R