Xilinx Virtex-4 ML461 User Manual page 59

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Table A-1: FPGA #1 Pinout (Continued)
Signal Name
DDR1_DIMM_DQ_BY1_B7
DDR1_DIMM_DQ_BY2_B0
DDR1_DIMM_DQ_BY2_B0_N
DDR1_DIMM_DQ_BY2_B1
DDR1_DIMM_DQ_BY2_B2
DDR1_DIMM_DQ_BY2_B2_N
DDR1_DIMM_DQ_BY2_B3
DDR1_DIMM_DQ_BY2_B3_N
DDR1_DIMM_DQ_BY2_B4
DDR1_DIMM_DQ_BY2_B5
DDR1_DIMM_DQ_BY2_B6
DDR1_DIMM_DQ_BY2_B7
DDR1_DIMM_DQ_BY3_B0
DDR1_DIMM_DQ_BY3_B1
DDR1_DIMM_DQ_BY3_B2
DDR1_DIMM_DQ_BY3_B2_N
DDR1_DIMM_DQ_BY3_B3
DDR1_DIMM_DQ_BY3_B4
DDR1_DIMM_DQ_BY3_B5
DDR1_DIMM_DQ_BY3_B6
DDR1_DIMM_DQ_BY3_B7
DDR1_DIMM_DQ_BY4_B0
DDR1_DIMM_DQ_BY4_B0_N
DDR1_DIMM_DQ_BY4_B1
DDR1_DIMM_DQ_BY4_B1_N
DDR1_DIMM_DQ_BY4_B2
DDR1_DIMM_DQ_BY4_B2_N
DDR1_DIMM_DQ_BY4_B3
DDR1_DIMM_DQ_BY4_B3_N
DDR1_DIMM_DQ_BY4_B4
DDR1_DIMM_DQ_BY4_B5
DDR1_DIMM_DQ_BY4_B6
DDR1_DIMM_DQ_BY4_B7
DDR1_DIMM_DQ_BY5_B0
DDR1_DIMM_DQ_BY5_B1
DDR1_DIMM_DQ_BY5_B2
DDR1_DIMM_DQ_BY5_B3
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
DDR1 DIMM Memory Interface (cont'd)
B9 DDR1_DIMM_DQ_BY5_B4
J20 DDR1_DIMM_DQ_BY5_B5
K22 DDR1_DIMM_DQ_BY5_B6
G24 DDR1_DIMM_DQ_BY5_B6_N
J22 DDR1_DIMM_DQ_BY5_B7
J26 DDR1_DIMM_DQ_BY6_B0
J23 DDR1_DIMM_DQ_BY6_B0_N
K21 DDR1_DIMM_DQ_BY6_B1
G26 DDR1_DIMM_DQ_BY6_B2
G25 DDR1_DIMM_DQ_BY6_B3
H24 DDR1_DIMM_DQ_BY6_B4
H23 DDR1_DIMM_DQ_BY6_B5
C23 DDR1_DIMM_DQ_BY6_B6
D23 DDR1_DIMM_DQ_BY6_B7
G20 DDR1_DIMM_DQ_BY7_B0
C26 DDR1_DIMM_DQ_BY7_B1
H20 DDR1_DIMM_DQ_BY7_B2
F26 DDR1_DIMM_DQ_BY7_B3
E26 DDR1_DIMM_DQ_BY7_B4
H22 DDR1_DIMM_DQ_BY7_B5
H21 DDR1_DIMM_DQ_BY7_B6
AA26 DDR1_DIMM_DQ_BY7_B6_N
Y26 DDR1_DIMM_DQ_BY7_B7
AB26 DDR1_DIMM_DQ_BY8_B0
Y25 DDR1_DIMM_DQ_BY8_B1
AB25 DDR1_DIMM_DQ_BY8_B2
V20 DDR1_DIMM_DQ_BY8_B3
AB24 DDR1_DIMM_DQ_BY8_B4
W20 DDR1_DIMM_DQ_BY8_B5
AC24 DDR1_DIMM_DQ_BY8_B6
AC23 DDR1_DIMM_DQ_BY8_B7
AD23 DDR1_DIMM_DQ_BY9_B0
AD22 DDR1_DIMM_DQ_BY9_B1
W19 DDR1_DIMM_DQ_BY9_B2
Y19 DDR1_DIMM_DQ_BY9_B3
AA19 DDR1_DIMM_DQ_BY9_B4
AA20 DDR1_DIMM_DQ_BY9_B4_N
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FPGA #1 Pinout
Signal Name Pin
AE24
AF24
AE23
Y20
AF23
AA10
AC7
Y10
AC8
AD8
AE9
AF9
AD6
AE6
AD1
AD2
AE3
AF3
AC3
AD3
AF5
AA7
AF6
H8
H7
E4
D3
G2
G1
F3
F4
H4
H3
H2
H1
J7
L7
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