Operation Example Of The 64128Efcbc-3Lp - Xilinx Virtex-4 ML461 User Manual

R
physical operating parameters of the LCD through register bit settings, controlling the
operating voltage, and the electronic volume level.
The voltage and contrast settings must be configured before the LCD panel is ready for
operation.
controller.

Operation Example of the 64128EFCBC-3LP

The KS0713 LCD controller has several default settings of operation on the LCD panel
display PCB. Some settings are forced through direct bonding on the chip. The default
settings are:
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Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Figure B-6 shows the initialization procedure required to set up the LCD
FPGA Configured and Application Running
ADC Select
- ADC = 0 SEG1 --> SEG132
- ADC = 1 SEG132 --> SEG1
SHL Select
- SHL = 0 COM1 --> COM64
- SHL = 1 COM64 --> COM1
Figure B-6: LCD Controller Initialization Flow
Master mode
Parallel mode
Internal oscillator
Duty cycle ratio is set to 1/65
Voltage converter input is between 2.4V ≤ VDD ≤ 3.6V, where VDD connects to 3.3V
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Setup Instruction Flow
Power ON
Board Power Supply Start
RESETB Pin is Kept Low
Start FPGA Configuration
RESETB Pin is Kept Low
RESETB Pin is Taken High
LCD Bias
ADC Select
DUTY0, 1 is "11"
SHL Select
LCD Bias 0 = 1/7
LCD Bias Select
LCD Bias 1 = 1/9
Voltage Converter ON
Wait longer than 1 ms between
Voltage Regulator ON
each instruction to let the voltages stabilize.
Voltage Follower ON
The on-chip resistors are used.
Regulator Resistor Select
Therefore, the selection MUST be
Set Reference Voltage
set to 101.
Setting Reference Voltage
End Initialization
is a two-pass instruction:
- Set Reference Voltage Mode
- Set Reference Voltage Register
Hardware Schematic Diagram
ug079_b_06_082807
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