Xilinx Virtex-4 ML461 User Manual page 24

Chapter 3: Hardware Description
Table 3-6: QDR II Component Signal Summary
Board Signal Name(s)
QDR2_SA[17:0]
QDR2_CK_BY0_3_[P,N],
QDR2_CK_BY4_7_[P,N]
QDR2_[R,W]_N
QDR2_D_BY[3:0]_B[8:0],
QDR2_K_BY0_3_[P,N],
QDR2_BW_BY[3:0]
QDR2_Q_BY[3:0]_B[8:0],
QDR2_CQ_BY0_3_[P,N]
QDR2_D_BY[7:4]_B[8:0],
QDR2_K_BY4_7_[P,N],
QDR2_BW_BY[3:0]
QDR2_Q_BY[7:4]_B[8:0],
QDR2_CQ_BY4_7_[P,N]
A copy of XAPP703: "QDR-2 SRAM Interface" and the corresponding reference design RTL
code are included on the CD shipped with the ML461 Tool Kit.
Table 3-7
Table 3-7: FCRAM II Component Signal Summary
Board Signal Name(s)
FCR2_A[13:0]
FCR2_CK[1:0] _[P,N]
FCR2_CS[1:0]_N, FCR2_FN,
FCR2_PD_N
FCR2_DQ_BY[1:0]_B[8:0],
FCR2_DS_BY0_1,
FCR2_QS_BY0_1
FCR2_DQ_BY[3:2]_B[8:0],
FCR2_DS_BY2_3,
FCR2_QS_BY2_3
For a complete list of FPGA #3 signals and their pin locations, refer to
Pinouts."
24
Bits
18 QDR II Address
4 QDR II Differential Clock
2 QDR II Control Signals
42 QDR II Write Data, Strobes, and Byte Write:
Bytes 3:0
38 QDR II Read Data and Strobes: Bytes 3:0
42 QDR II Write Data, Strobes, and Byte Write:
Bytes 7:4
38 QDR II Read Data and Strobes: Bytes 7:4
describes all signals associated with FCRAM-II Component memories.
Bits
14 FCRAM II Address
4 FCRAM II Differential Clock
4 FCRAM II Control Signals
20 FCRAM II Data and Strobes: Bytes 1:0
20 FCRAM II Data and Strobes: Bytes 3:2
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Description
Description
Virtex-4 ML461 Development Board User Guide
Schematic
Bank #
Page #
8 59
8 59
8 59
7, 9 58
7, 9 58
8, 10 59
8, 10 59
Schematic
Bank #
Page #
5 54
5 54
5 54
6 55
5 54
Appendix A, "FPGA
UG079 (v1.1) September 5, 2007
R