Xilinx Virtex-4 ML461 User Manual page 73

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Table A-3: FPGA #3 Pinout (Continued)
Signal Name
QDR2_SA7
QDR2_SA8
QDR2_SA9
QDR2_SA10
QDR2_SA11
QDR2_SA12
FCR2_A0
FCR2_A1
FCR2_A2
FCR2_A3
FCR2_A4
FCR2_A5
FCR2_A6
FCR2_A7
FCR2_A8
FCR2_A9
FCR2_A10
FCR2_A11
FCR2_A12
FCR2_A13
FCR2_BA0
FCR2_BA1
FCR2_CK0_N
FCR2_CK0_P
FCR2_CK1_N
FCR2_CK1_P
FCR2_CS0_N
FCR2_CS1_N
FCR2_DQ_BY0_B0
FCR2_DQ_BY0_B1
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
QDR II Memory Interface (cont'd)
Y10 QDR2_SA13
AA10 QDR2_SA14
AC7 QDR2_SA15
AC9 QDR2_SA16
AB9 QDR2_SA17
AE6 QDR2_W_N
FCRAM II Memory Interface
A22 FCR2_DQ_BY0_B2
A21 FCR2_DQ_BY0_B3
D24 FCR2_DQ_BY0_B4
C24 FCR2_DQ_BY0_B5
G19 FCR2_DQ_BY0_B6
F19 FCR2_DQ_BY0_B7
E23 FCR2_DQ_BY0_B8
E22 FCR2_DQ_BY1_B0
F20 FCR2_DQ_BY1_B1
E20 FCR2_DQ_BY1_B2
D23 FCR2_DQ_BY1_B3
C23 FCR2_DQ_BY1_B4
H20 FCR2_DQ_BY1_B5
G20 FCR2_DQ_BY1_B6
H22 FCR2_DQ_BY1_B7
H21 FCR2_DQ_BY1_B8
F23 FCR2_DQ_BY2_B0
F24 FCR2_DQ_BY2_B1
D25 FCR2_DQ_BY2_B2
D26 FCR2_DQ_BY2_B3
F26 FCR2_DQ_BY2_B4
E26 FCR2_DQ_BY2_B5
D10 FCR2_DQ_BY2_B6
C10 FCR2_DQ_BY2_B7
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FPGA #3 Pinout
Signal Name Pin
AD6
AF9
AE9
AD8
AC8
AF6
D9
C8
A8
A7
F10
E10
A6
G10
G9
F8
G8
B7
C7
A9
B9
A3
C17
D17
C20
B20
B18
A18
E17
F17
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