Jtag Chain; Jtag Port - Xilinx Virtex-4 ML461 User Manual

Chapter 6: Configuration

JTAG Chain

Five devices (the System ACE chip and four XC4VLX25-FF668 FPGAs) are connected via a
JTAG chain on the Virtex-4 ML461 Development Board. The order of the five devices in the
JTAG chain is System ACE chip (U36), FPGA #1 (U15), FPGA #2 (U14), FPGA #3 (U23), and
FPGA #4 (U33). The DONE pin of the FPGAs in the chain are tied together to a single LED
(D1). Each FPGA in the JTAG chain must be programmed for the board to be configured
properly. A blank design can be used to program FPGAs in the JTAG chain that do not
need functionality.
Three different sources can be used to drive this JTAG chain:
•
•
•

JTAG Port

The Virtex-4 ML461 Development Board provides a JTAG connector (P65) that can be used
to program the Virtex-4 FPGAs, and program and/or configure other JTAG devices in the
chain.
Development Board.
54
Figure 6-1: Configuration Mode Switch
JTAG Port
Xilinx Parallel Cable IV
System ACE controller
Figure 6-2 shows the pin assignments for the JTAG connector on the Virtex-4 ML461
TSTTDO
TSTTDI
TSTTCK
TSTTMS
HALTB
Figure 6-2: JTAG Connector P65
www.xilinx.com
SW1
MODE
ug079_c6_01_080105
P65 JTAG
Connector
1 2
TRSTB
3 4
3.3V
5 6
7 8
9 10
11 12
13 14
GND
15 16
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Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
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