Xilinx Virtex-4 ML461 User Manual page 19

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Table 3-3
Table 3-3: DDR400 Component Signal Summary
Board Signal Name(s)
DDR1_A[12:0]
DDR1_CK[3:0]_[P,N]
DDR1_[RAS,CAS,WE]_N, DDR1_CKE,
DDR1_BA[1:0], DDR1_CS[3:0]_N,
DDR1_DM_BY[3:0]
DDR1_DQ_BY0_B[3:0],
DDR1_DQS_BY0_L_P
DDR1_DQ_BY1_B[7:0],
DDR1_DQS_BY1_P
DDR1_DQ_BY2_B[7:0],
DDR1_DQS_BY2_P
DDR1_DQ_BY3_B[7:0],
DDR1_DQS_BY3_P
Notes:
1. DDR1_CKE is connected to a 4.7K pull-down resistor.
A copy of XAPP709: "DDR SDRAM Controller Using Virtex-4 FPGA Devices" and its
corresponding reference design RTL code are included on the CD shipped with the ML461
Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to
A, "FPGA Pinouts."
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
describes all signals associated with DDR400 Component memories.
Bits
13 DDR400 Component Address
8 DDR400 Component Differential Clock
14 DDR400 Component Control Signals
5 DDR400 Data and Strobe: Byte 0
9 DDR400 Data and Strobe: Byte 1
9 DDR400 Data and Strobe: Byte 2
9 DDR400 Data and Strobe: Byte 3
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Description
Memory Interfaces
Bank Schematic
# Page #
1 4
2 4
2, 10 4, 10
6 8
6 8
6 8
6 8
Appendix
19