Xilinx Virtex-4 ML461 User Manual page 62

Appendix A: FPGA Pinouts
Table A-1: FPGA #1 Pinout (Continued)
Signal Name
DDR1_DQ_BY2_B0
DDR1_DQ_BY2_B1
DDR1_DQ_BY2_B2
DDR1_DQ_BY2_B3
DDR1_DQ_BY2_B4
DDR1_DQ_BY2_B5
DDR1_DQ_BY2_B6
DDR1_DQ_BY2_B7
DDR1_DQ_BY3_B0
DDR1_DQ_BY3_B1
DDR1_DQ_BY3_B2
SYNTH_CLK_TO_FPGA1_N
SYNTH_CLK_TO_FPGA1_P
EXT_CLK_TO_FPGA1_N
FPGA4_FPGA1_MII_TX_CLK
FPGA4_FPGA1_MII_TX_DATA_B0
FPGA4_FPGA1_MII_TX_DATA_B1
FPGA4_FPGA1_MII_TX_DATA_B2
FPGA4_FPGA1_MII_TX_DATA_B3
FPGA4_FPGA1_MII_TX_EN
FPGA4_FPGA1_MII_TX_ERR
FPGA4_FPGA1_MII_TX_SPARE
FPGA_CCLK
FPGA_CNFG_M0
FPGA_CNFG_M1
FPGA_CNFG_M2
FPGA_DIN
FPGA_DONE
FPGA_INIT
FPGA1_TEST_HDR_B0
FPGA1_TEST_HDR_B1
62
Pin
DDR1 Component Memory Interface (cont'd)
M25
M24
M21
M20
M23
M22
N25
N24
R8
R7
V4
FPGA #1 Clock Signals
C14
C15
B14
FPGA #1 MII Link Interface
AF12
AB10
AB17
AC17
AF11
AE12
AC10
AF10
FPGA #1 Configuration Signals
G14
W15
Y15
W14
G12
H14
G15
FPGA #1 Test Header Signals
A12
A11
FPGA #1 Test Header Signals (cont'd)
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Signal Name
DDR1_DQ_BY3_B3
DDR1_DQ_BY3_B4
DDR1_DQ_BY3_B5
DDR1_DQ_BY3_B6
DDR1_DQ_BY3_B7
DDR1_RAS_N
DDR1_READ_VALID_LOOPBACK
DDR1_READ_VALID_LOOPBACK
DDR1_READ_VALID_LOOPBACK_BANK9
DDR1_READ_VALID_LOOPBACK_BANK9
DDR1_WE_N
EXT_CLK_TO_FPGA1_P
DIRECT_CLK_TO_FPGA1_N
DIRECT_CLK_TO_FPGA1_P
FPGA1_FPGA4_MII_TX_CLK
FPGA1_FPGA4_MII_TX_DATA_B0
FPGA1_FPGA4_MII_TX_DATA_B1
FPGA1_FPGA4_MII_TX_DATA_B2
FPGA1_FPGA4_MII_TX_DATA_B3
FPGA1_FPGA4_MII_TX_EN
FPGA1_FPGA4_MII_TX_ERR
FPGA1_FPGA4_MII_TX_SPARE
FPGA_PROGB
FPGA_TCK
FPGA_TDO
FPGA_TMS
FPGA_VBATT
SYS_RESET_IN_N
FPGA1_TEST_HDR_B2
FPGA1_TEST_HDR_B3
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
U4
T8
U7
U6
U5
AA12
D8
F10
J21
L26
AC16
B15
A15
A16
AE14
AD10
AD17
AD16
AD12
AE13
AE10
AD11
H15
W12
Y13
Y11
Y16
K1
B13
B12