Xilinx Virtex-4 ML461 User Manual page 31

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Table 3-12: FPGA #4 Signals for Voltage Margining (Continued)
Notes:
1. The schematics on the CD have a typographical error in signal naming. The VMARGIN_UP_xxxx_N
Table 3-13: Voltage Margining
Note:
1. If both of the voltage-margining inputs to the power regulator are pulled Low, the output voltage will
2. To control the voltage levels using FPGA #4, make sure there are no jumpers connecting the header
3. Three-pin jumpers on the board connect to these module input pins: P11, P12, P28, P29, P39.
Table 3-14: Header Connections and Voltage
Another module I/O allows the output voltages of two related power planes to track.
Tying pin 8 (TRACK) of two or more power modules together guarantees that these
voltages will come up together at power-up. (This feature has not been tested on the
Virtex-4 ML461 Development Board, although there is a provision to do so by populating
some 0Ω resistors.)
The module output also can be enabled or inhibited through the use of on-board two-pin
jumpers (P18, P20, P34, P36, P52, P63). The inhibit jumpers use the following conventions:
•
•
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Power Plane
VCC2V5
VCC3V3
signals are connected to the DN_N input (pin 9) on the PTH05010 modules and vice versa for the
UP_N input (pin 10). When this control function is implemented, the code within FPGA #4 accounts
for swapping the functionality of these pins.
VMARGIN_UP
Open
Open
Low
Low
be close to nominal but results in the possibility of a slightly higher error in the output voltage. The
power modules use a low-leakage "open-drain" control signal to control the voltage margining. In the
FPGA, this can be approximated by using a control signal that drives the output low when active and
does not drive the signal at all when inactive (high impedance output).
pins listed in Table (table added for headers below).
Connection on Headers
None
2 – 3
1 – 2
Jumper OFF = Enabled
Jumper ON = Inhibited
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Signal Name
VMARGIN_UP_VCC2V5_N
VMARGIN_DN_VCC2V5_N
VMARGIN_UP_VCC3V3_N
VMARGIN_DN_VCC3V3_N
VMARGIN_DN
Open
Low
Open
Low
Voltage
Nominal
-5%
+5%
Characterization
Pin
P20
P19
T23
R20
Output Voltage
Nominal
-5%
+5%
Undefined
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