Xilinx Virtex-4 ML461 User Manual page 61

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Table A-1: FPGA #1 Pinout (Continued)
Signal Name
DDR1_DIMM_DQ_CB0_7_B4_N
DDR1_DIMM_DQ_CB0_7_B5
DDR1_DIMM_DQ_CB0_7_B5_N
DDR1_DIMM_DQ_CB0_7_B6
DDR1_DIMM_DQ_CB0_7_B6_N
DDR1_DIMM_DQ_CB0_7_B7
DDR1_DIMM_DQ_CB8_15_B0
DDR1_DIMM_DQ_CB8_15_B1
DDR1_DIMM_DQ_CB8_15_B2
DDR1_DIMM_DQ_CB8_15_B3
DDR1_DIMM_DQ_CB8_15_B3_N
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_BA0
DDR1_BA1
DDR1_BY0_CS0_N
DDR1_BY0_CS1_N
DDR1_BY1_CS_N
DDR1_BY2_3_CS_N
DDR1_CAS_N
DDR1_CK0_N
DDR1_CK0_P
DDR1_CK1_N
DDR1_CK1_P
DDR1_CK2_N
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
DDR1 DIMM Memory Interface (cont'd)
R26 DDR1_DIMM_DQ_CB8_15_B4
P23 DDR1_DIMM_DQ_CB8_15_B5
N21 DDR1_DIMM_DQ_CB8_15_B6
P22 DDR1_DIMM_DQ_CB8_15_B7
N20 DDR1_DIMM_RESET_N
R23 DDR1_DIMM_SA0
U22 DDR1_DIMM_SA1
U21 DDR1_DIMM_SA2
U23 DDR1_DIMM_SCL
V23 DDR1_DIMM_SDA
U25 DDR1_DIMM_WE_N
DDR1 Component Memory Interface
D12 DDR1_CK2_P
E13 DDR1_CK3_N
D11 DDR1_CK3_P
C11 DDR1_CKE
E14 DDR1_DM_BY0
D15 DDR1_DM_BY1
D14 DDR1_DM_BY2
F15 DDR1_DM_BY3
F16 DDR1_DQS_BY0_L_N
F11 DDR1_DQS_BY0_L_P
D16 DDR1_DQS_BY1_P
F12 DDR1_DQS_BY2_P
F13 DDR1_DQS_BY3_P
AC13 DDR1_DQ_BY0_B0
AD13 DDR1_DQ_BY0_B1
G19 DDR1_DQ_BY0_B2
F19 DDR1_DQ_BY0_B3
E23 DDR1_DQ_BY1_B0
E22 DDR1_DQ_BY1_B1
AA11 DDR1_DQ_BY1_B2
AB14 DDR1_DQ_BY1_B3
AA14 DDR1_DQ_BY1_B4
AC11 DDR1_DQ_BY1_B5
AC12 DDR1_DQ_BY1_B6
AA15 DDR1_DQ_BY1_B7
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FPGA #1 Pinout
Signal Name Pin
V26
V25
T21
T20
L1
L3
M8
L8
K2
L4
M5
AA16
AD14
AC14
AC15
J2
K3
M2
M1
A7
A8
K26
M19
U1
D9
C8
C10
D10
L19
K20
L21
L20
K24
K23
L24
L23
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