Memory Interfaces - Xilinx Virtex-4 ML461 User Manual

Chapter 3: Hardware Description

Memory Interfaces

Table 3-1
various memory types. The maximum speed goal is based on using faster speed grade
XC4VLX25-FF668-12 devices.
Table 3-1: Summary of ML461 Memory Interfaces
Memory Type
DDR2 DIMM
DDR2 SDRAM
DDR1 DIMM
DDR1 SDRAM
QDR II
RLDRAM II
When a memory with a larger data/strobe ratio is implemented, for example, a x36 QDR II
device, the smaller configurations can also be demonstrated by programming the FPGA
for a smaller data width, such as a 9:1 data/strobe ratio for the QDR II device.
Figure 3-2
showing connectivity between the memory types and the four XC4VLX25-FF668 FPGAs.
The conventions for showing multiple loads on a net are as follows:
•
•
14
summarizes the implementation of the Virtex-4 ML461 Development Board for
Maximum
Data Rate
Speed
267 MHz 533 Mb/s
267 MHz 533 Mb/s
200 MHz 400 Mb/s
200 MHz 400 Mb/s
300 MHz 1.2 Gb/s
300 MHz 600 Mb/s
illustrates a detailed block diagram of the Virtex-4 ML461 Development Board
stacks of devices are shown with overlapping blocks, such as two x4 devices for the
DDR1 component interface
multiple signals are on the same arrow, such as Address/Control signals to most of
the memories
www.xilinx.com
Data Width I/O Standard
144 SSTL18
28 SSTL18
144 SSTL2
28 SSTL2
72 HSTL
36 HSTL Class II
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Data/Strobe
Ratios
4:1, 8:1
4:1, 8:1
4:1, 8:1
4:1, 8:1
18:1, 36:1
9:1, 18:1