Xilinx Virtex-4 ML461 User Manual page 34

Memory interfaces
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Chapter 3: Hardware Description
TOP
GND1
PWR1
InnerSignal1
GND1a
InnerSignal2
GND2
PWR2
InnerSignal3
InnerSignal4
GND4
PWR3
InnerSignal5
GND5a
InnerSignal6
GND5
PWR4
BOTTOM
Table 3-15
the controlled impedance values for the signal layers.
34
Total Thickness = 98.67 mils
Figure 3-10: ML461 Revision B PCB Stack-up
shows the details of the dielectric material and construction for each layer and
www.xilinx.com
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
1.3 mils
1.338 mils
4 mils
1.338 mils
4 mils
1.338 mils
5 mils
0.669 mils
5 mils
1.338 mils
5 mils
0.669 mils
5 mils
1.338 mils
4 mils
1.338 mils
4 mils
0.669 mils
4 mils
0.669 mils
4 mils
1.338 mils
4 mils
1.338 mils
5 mils
0.669 mils
5 mils
1.338 mils
5 mils
0.669 mils
5 mils
1.338 mils
4 mils
1.338 mils
4 mils
1.338 mils
1.3 mils
UG079_c3_10_072905

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