Xilinx Virtex-4 ML461 User Manual page 68

Appendix A: FPGA Pinouts
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
DDR2_DIMM_RESET_N
DDR2_DIMM_SA0
DDR2_DIMM_SA1
DDR2_DIMM_SA2
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A13
DDR2_BA0
DDR2_BA1
DDR2_BY0_CS0_N
DDR2_BY0_CS1_N
DDR2_BY1_CS_N
DDR2_BY2_3_CS_N
DDR2_CAS_N
DDR2_CK0_N
DDR2_CK0_P
DDR2_CK1_N
DDR2_CK1_P
DDR2_CK2_N
DDR2_CK2_P
DDR2_CK3_N
DDR2_CK3_P
DDR2_CKE
DDR2_DM_BY0
DDR2_DM_BY1
DDR2_DM_BY2
68
Pin
DDR2 DIMM Memory Interface (cont'd)
L1 DDR2_DIMM_SCL
B10 DDR2_DIMM_SDA
A10 DDR2_DIMM_WE_N
B12
DDR2 Component Memory Interface
E13 DDR2_DM_BY3
D11 DDR2_DQS_BY0_L_N
C11 DDR2_DQS_BY0_L_P
E14 DDR2_DQS_BY1_N
D15 DDR2_DQS_BY1_P
F15 DDR2_DQS_BY2_N
F16 DDR2_DQS_BY2_P
F11 DDR2_DQS_BY3_N
F12 DDR2_DQS_BY3_P
D16 DDR2_DQ_BY0_B0
F13 DDR2_DQ_BY0_B1
F14 DDR2_DQ_BY0_B2
C16 DDR2_DQ_BY0_B3
AD13 DDR2_DQ_BY1_B0
AC13 DDR2_DQ_BY1_B1
G19 DDR2_DQ_BY1_B2
F19 DDR2_DQ_BY1_B3
E23 DDR2_DQ_BY1_B4
E22 DDR2_DQ_BY1_B5
AA11 DDR2_DQ_BY1_B6
AB14 DDR2_DQ_BY1_B7
AA14 DDR2_DQ_BY2_B0
AC11 DDR2_DQ_BY2_B1
AC12 DDR2_DQ_BY2_B2
AA15 DDR2_DQ_BY2_B3
AA16 DDR2_DQ_BY2_B4
AD14 DDR2_DQ_BY2_B5
AC14 DDR2_DQ_BY2_B6
AC16 DDR2_DQ_BY2_B7
J2 DDR2_DQ_BY3_B0
K3 DDR2_DQ_BY3_B1
M2 DDR2_DQ_BY3_B2
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
A17
B17
M5
M1
A7
A8
K25
K26
N19
M19
T1
U1
D9
C8
C10
D10
L19
K20
L21
L20
K24
K23
L24
L23
M25
M24
M21
M20
M23
M22
N25
N24
R8
R7
V4