Xilinx Virtex-4 ML461 User Manual page 21

R
Table 3-4: DDR2 DIMM Signal Summary
Board Signal Name(s)
DDR2_DIMM_A[12:0]
DDR2_DIMM_CK[5:0]_[P,N]
DDR2_DIMM_[RAS,CAS,WE]_N,
DDR2_DIMM_CKE, DDR2_DIMM_BA[1:0],
DDR2_DIMM_CS[3:0]_N,
DDR2_DIMM_BY0_7_ODT,
DDR2_DIMM_BY8_15_ODT,
DDR2_DIMM_DQ_BY[0,1,8,9]_B[7:0],
DDR2_DIMM_DQS_BY[0,1,8,9]_L_[P,N],
DDR2_DIMM_DM_DQS_BY[0,1,8,9]_H_[P,N]
DDR2_DIMM_DQ_BY[2,3,10,11]_B[7:0],
DDR2_DIMM_DQS_BY[2,3,10,11]_L_[P,N],
DDR2_DIMM_DM_DQS_BY[2,3,10,11]_H_[P,N]
DDR2_DIMM_DQ_BY[4,5,12,13]_B[7:0],
DDR2_DIMM_DQS_BY[4,5,12,13]_L_[P,N],
DDR2_DIMM_DM_DQS_BY[4,5,12,13]_H_[P,N]
DDR2_DIMM_DQ_BY[6,7,14,15]_B[7:0],
DDR2_DIMM_DQS_BY[6,7,14,15]_L_[P,N],
DDR2_DIMM_DM_DQS_BY[6,7,14,15]_H_[P,N]
DDR2_DIMM_DQ_CB0_7_B[7:0],
DDR2_DIMM_DQS_CB0_7_L_[P,N],
DDR2_DIMM_DM_DQS_CB0_7_H_[P,N]
DDR2_DIMM_DQ_CB8_15_B[7:0],
DDR2_DIMM_DQS_CB8_15_L_[P,N],
DDR2_DIMM_DM_DQS_CB8_15_H_[P,N]
Notes:
1. DDR2_DIMM_CKE, DDR2_DIMM_BY0_7_ODT, and DDR2_DIMM_BY8_18_ODT signals are connected to a 4.7K pull-down
resistor.
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Bits Description
13 DDR2 DIMM Address
12 DDR2 DIMM Differential Clock
10 DDR2 DIMM Control Signals
48 DDR2 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
48 DDR2 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
48 DDR2 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
48 DDR2 DIMM Data and Strobes:
Bytes 6, 7, 14, 15
12 DDR2 DIMM Data and Strobes:
Check Byte 0
12 DDR2 DIMM Data and Strobes:
Check Byte 1
www.xilinx.com
Memory Interfaces
Bank Schematic
# Page #
10 34
10 34
10 34
5 31
6 32
8 35
7 36
9 33
9 33
21