Array Connector Numbering; Ucf Information - Xilinx Virtex-4 ML461 User Manual

R

Array Connector Numbering

A B C
10
9
8
7
6
5
4
3
2
1
Connector J32

UCF Information

Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Bank 0
D E F G H I
Figure B-12: LCD Connections (Bank 0)
# FPGA 4
# Bank 7 / LCD-BUS
#
# NET " " LOC ="Y21 "; # LCD_D7 IO_L20N_VREF_7
# NET " " LOC ="Y20 "; # LCD_D6 IO_L20P_7
# NET " " LOC ="AE23 "; # LCD_D5 IO_L19N_7
# NET " " LOC ="AF23 "; # LCD_D4 IO_L19P_7
# NET " " LOC ="W19 "; # LCD_D3 IO_L18N_7
# NET " " LOC ="Y19 "; # LCD_D2 IO_L18P_7
# NET " " LOC ="AF20 "; # LCD_D1 IO_L17N_7
# NET " " LOC ="AF19 "; # LCD_D0 IO_L17P_7
# NET " " LOC ="AA18 "; # LCD_RS IO_L21P_7
# NET " " LOC ="Y18 "; # LCD_RW IO_L21N_7
# NET " " LOC ="AF24 "; # LCD_ENA IO_L22P_7
# NET " " LOC ="AE24 "; #LCD_BL_ON IO_L22N_7
# NET " " LOC ="AE20 "; # LCD_CS1B IO_L23P_VRN_7
# NET " " LOC ="AD20 "; # LCD_RSEL IO_L23N_VRP_7
#
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Hardware Schematic Diagram
Connector Pin
D9 LCD_D0
D7 LCD_D4
D5 LCD_D5
D3 LCD_D6
D1 LCD_D7
E10 LCD_RST
E8 LCD_D1
E6 LCD_D2
E4 LCD_D3
E2 LCD_ENA
F5 LCD_R/W
F3 LCD_RSEL
F1 LCD_CS1B
FPGA Pin
AF19
AF23
AE23
Y20
Y21
AA18
AF20
Y19
W19
AF24
Y18
AD20
AE20
UG079_B_12_081005
105