Xilinx Virtex-4 ML461 User Manual page 50

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Table 5-1
ML461 Development Board for the following seven different memory interfaces:
1.
2.
3.
4.
5.
6.
7.
Table 5-1: DDR1 SDRAM DIMM Terminations
Signal
Data (DQ)
Data Strobe (DQS)
6 pairs of Clocks (CK, CK), 3
each per DIMM
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE and others)
Table 5-2: DDR1 SDRAM Components Terminations
Signal
Data (DQ)
Data Strobe (DQS)
Clock (CK, CK)
Address (A, BA)
Control (RAS, CAS, WE,
CS, CKE)
50
through Table 5-7 summarize the termination schemes used on the Virtex-4
DDR1 SDRAM DIMM
DDR1 SDRAM Components
DDR2 SDRAM DIMM
DDR2 SDRAM Components
QDR-II SRAM
FCRAM-II SDRAM
RLDRAM-II SDRAM
FPGA Driver Termination at FPGA
SSTL2_II 50Ω pull-up to 1.3V
SSTL2_II 50Ω pull-up to 1.3V
SSTL2_II No termination
SSTL2_II No termination
SSTL2_II No termination
FPGA Driver Termination at FPGA
SSTL2_II 50Ω pull-up to 1.3 V
SSTL2_II 50Ω pull-up to 1.3 V
SSTL2_II No termination
SSTL2_II No termination
SSTL2_II No termination
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Termination at Memory
50Ω pull-up to 1.3V
50Ω pull-up to 1.3V
100Ω differential termination between
pair
50Ω pull-up to 1.3V after the second
DIMM
50Ω pull-up to 1.3V after the second
DIMM
Termination at Memory
50Ω pull-up to 1.3V
50Ω pull-up to 1.3V
100Ω differential termination between
pair
50Ω pull-up to 1.3V after the last
component
50Ω pull-up to 1.3V after the last
component
Virtex-4 ML461 Development Board
UG079 (v1.1) September 5, 2007