Fpga #2 Pinout - Xilinx Virtex-4 ML461 User Manual

Appendix A: FPGA Pinouts

FPGA #2 Pinout

Table A-2
Table A-2: FPGA #2 Pinout
Signal Name
DDR2_DIMM_A0
DDR2_DIMM_A1
DDR2_DIMM_A2
DDR2_DIMM_A3
DDR2_DIMM_A4
DDR2_DIMM_A5
DDR2_DIMM_A6
DDR2_DIMM_A7
DDR2_DIMM_A8
DDR2_DIMM_A9
DDR2_DIMM_A10
DDR2_DIMM_A11
DDR2_DIMM_A12
DDR2_DIMM_A13
DDR2_DIMM_BA0
DDR2_DIMM_BA1
DDR2_DIMM_BA2
DDR2_DIMM_BY0_7_CK0_N
DDR2_DIMM_BY0_7_CK0_P
DDR2_DIMM_BY0_7_CK1_N
DDR2_DIMM_BY0_7_CK1_P
DDR2_DIMM_BY0_7_CK2_N
DDR2_DIMM_BY0_7_CK2_P
DDR2_DIMM_BY0_7_CS_N
DDR2_DIMM_BY0_7_ODT
DDR2_DIMM_BY8_15_CK0_N
DDR2_DIMM_BY8_15_CK0_P
DDR2_DIMM_BY8_15_CK1_N
DDR2_DIMM_BY8_15_CK1_P
DDR2_DIMM_BY8_15_CK2_N
DDR2_DIMM_BY8_15_CK2_P
DDR2_DIMM_BY8_15_CS_N
DDR2_DIMM_BY8_15_ODT
DDR2_DIMM_CAS_N
64
lists the connections for FPGA #2 (U15).
Pin
DDR2 DIMM Memory Interface
Y9 DDR2_DIMM_CKE
AA9 DDR2_DIMM_DM_DQS_BY0_H_N
V1 DDR2_DIMM_DM_DQS_BY0_H_P
V2 DDR2_DIMM_DM_DQS_BY1_H_N
T6 DDR2_DIMM_DM_DQS_BY1_H_P
T7 DDR2_DIMM_DM_DQS_BY2_H_N
T3 DDR2_DIMM_DM_DQS_BY2_H_P
T4 DDR2_DIMM_DM_DQS_BY3_H_N
U3 DDR2_DIMM_DM_DQS_BY3_H_P
R4 DDR2_DIMM_DM_DQS_BY4_H_N
AD5 DDR2_DIMM_DM_DQS_BY4_H_P
M6 DDR2_DIMM_DM_DQS_BY5_H_N
M4 DDR2_DIMM_DM_DQS_BY5_H_P
AD4 DDR2_DIMM_DM_DQS_BY6_H_N
Y8 DDR2_DIMM_DM_DQS_BY6_H_P
AA8 DDR2_DIMM_DM_DQS_BY7_H_N
R2 DDR2_DIMM_DM_DQS_BY7_H_P
N4 DDR2_DIMM_DM_DQS_BY8_H_N
N5 DDR2_DIMM_DM_DQS_BY8_H_P
M7 DDR2_DIMM_DM_DQS_BY9_H_N
N7 DDR2_DIMM_DM_DQS_BY9_H_P
N8 DDR2_DIMM_DM_DQS_BY10_H_N
P8 DDR2_DIMM_DM_DQS_BY10_H_P
N3 DDR2_DIMM_DM_DQS_BY11_H_N
F20 DDR2_DIMM_DM_DQS_BY11_H_P
P2 DDR2_DIMM_DM_DQS_BY12_H_N
P3 DDR2_DIMM_DM_DQS_BY12_H_P
P4 DDR2_DIMM_DM_DQS_BY13_H_N
P5 DDR2_DIMM_DM_DQS_BY13_H_P
P6 DDR2_DIMM_DM_DQS_BY14_H_N
P7 DDR2_DIMM_DM_DQS_BY14_H_P
N2 DDR2_DIMM_DM_DQS_BY15_H_N
E20 DDR2_DIMM_DM_DQS_BY15_H_P
F1 DDR2_DIMM_DM_DQS_CB0_7_H_N
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Signal Name
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Pin
R1
A18
B18
E24
E25
H5
H6
K6
K7
W5
W6
AE4
AF4
AB22
AC22
Y18
AA18
A19
A20
H25
H26
C7
B7
D6
E7
AB5
AC5
AB9
AC9
AF20
AF19
AE18
AF18
P19