Design Examples; Lcd Panel Used In Full Graphics Mode - Xilinx Virtex-4 ML461 User Manual

Appendix B: LCD Interface
RS
RW
CS1B
E
WRITE
DB0-DB7
READ

Design Examples

LCD Panel Used in Full Graphics Mode

The LCD controller RAM has eight 132-byte pages (in fact, there are nine pages; page 9 is
special). Each page is one byte wide. If all the pages are put in one memory block, then the
needed space is 8 pages x 8 bits x 132 pixels or 8448 bits (1056 bytes).
One Virtex-4 block RAM can be configured as 8+1 by 2048.
One block RAM can be used to store one complete pixel view of the LCD panel. There is
enough space left for commands.
The ninth bit in the block RAM memory indicates whether the data in the block RAM is
real data to be displayed or is a command for the controller.
The interface to the LCD panel is slow. The E signal can be used as the controller clock
signal. This signal has a minimum cycle time of 400 ns for displaying 8 bits (equal to 8 dots)
on the LCD. One full page of the display takes up to 132 x 400 ns = 52.8 μs. Updating the
full display takes 52.8μs x 8 = 423μs.
If using the dual port and data width capabilities of the block RAM, then writes to the
block RAM can be 32 bits (+4 control bits), and reads from the block RAM on the LCD side
can be 8 bits (1 control bit). An entire LCD page is updated in 33 write operations.
The interface on the LCD panel side sequentially reads the block RAM, and thus, updates
the screen contiguously (like a television screen). The controller (microcontroller or other)
side of the block RAM can be written at any time.
100
T AS
T PWR
T ACC
Figure B-7: Read/Write Timing Waveforms (6800 Mode)
www.xilinx.com
T AH
T CYC
T PWW
T DS T DH
T OD
Virtex-4 ML461 Development Board User Guide
ug079_b_07_081005
UG079 (v1.1) September 5, 2007
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