Xilinx Virtex-4 ML461 User Manual page 18

Chapter 3: Hardware Description
Table 3-2: DDR1 DIMM Signal Summary
Board Signal Name(s)
DDR1_DIMM_A[12:0]
DDR1_DIMM_CK[5:0]_[P,N]
DDR1_DIMM_[RAS,CAS,WE]_N,
DDR1_DIMM_CKE, DDR1_DIMM_BA[1:0],
DDR1_DIMM_CS[3:0]_N,
DDR1_DIMM_DQ_BY[0,1,8,9]_B[7:0],
DDR1_DIMM_DQS_BY[0,1,8,9]_L_P,
DDR1_DIMM_DM_DQS_BY[0,1,8,9]_H_P
DDR1_DIMM_DQ_BY[2,3,10,11]_B[7:0],
DDR1_DIMM_DQS_BY[2,3,10,11]_L_P,
DDR1_DIMM_DM_DQS_BY[2,3,10,11]_H_P
DDR1_DIMM_DQ_BY[4,5,12,13]_B[7:0],
DDR1_DIMM_DQS_BY[4,5,12,13]_L_P,
DDR1_DIMM_DM_DQS_BY[4,5,12,13]_H_P
DDR1_DIMM_DQ_BY[6,7,14,15]_B[7:0],
DDR1_DIMM_DQS_BY[6,7,14,15]_L_P,
DDR1_DIMM_DM_DQS_BY[6,7,14,15]_H_P
DDR1_DIMM_DQ_CB0_7_B[7:0],
DDR1_DIMM_DQS_CB0_7_L_P,
DDR1_DIMM_DM_DQS_CB0_7_H_P
DDR1_DIMM_DQ_CB8_15_B[7:0],
DDR1_DIMM_DQS_CB8_15_L_P,
DDR1_DIMM_DM_DQS_CB8_15_H_P
Notes:
1. DDR1_DIMM_CKE is connected to a 4.7K pull-down resistor.
To use Registered DDR1 DIMMs with the ML461 memory board, it is necessary to connect
Pin 10 of socket XP2 (reset#) and drive this signal with FPGA1.
18
For example, DDR1_CK[3:0]_[P,N] represents 4 * 2 = 8 signals to fully expand two sets
of brackets. That is, the eight signals are: DDR1_CK3_P, DDR1_CK3_N, DDR1_CK2_P,
...., DDR1_CK0_N.
Bits
13
12
10
40
40
40
40
10
10
www.xilinx.com
Description
DDR1 DIMM Address
DDR1 DIMM Differential Clock
DDR1 DIMM Control Signals
DDR1 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
DDR1 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
DDR1 DIMM Data and Strobes:
Bytes 0, 1, 8, 9
DDR1 DIMM Data and Strobes:
Bytes 6, 7, 14, 15
DDR1 DIMM Data and Strobes:
Check Byte 0
DDR1 DIMM Data and Strobes:
Check Byte 1
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Schematic
Bank #
Page #
10 10
10 10
10 10
6 8
8 11
5 7
6 8
9 9
9 9