Xilinx Virtex-4 ML461 User Manual page 26

Chapter 3: Hardware Description
Table 3-8
Table 3-8: RLDRAM II Component Signal Summary
Board Signal Name(s)
RLD2_A[19:0], RLD2_BA[2:0]
RLD2_CK0_1 _[P,N]
RLD2_CK2_3 _[P,N]
RLD2_CS_BY[0_1,2_3]_N,
RLD2_[REF,WE]_N,
RLD2_DM_BY[0_1,2_3]_N,
RLD2_QVLD_BY[0_1]
RLD2_QVLD_BY[2_3]
RLD2_DQ_BY[1:0]_B[8:0],
RLD2_DK_BY0_1_[P,N],
RLD2_QK_BY[1:0]_[P,N]
RLD2_DQ_BY[3:2]_B[8:0],
RLD2_DK_BY0_1_[P,N],
RLD2_QK_BY[3:2]_[P,N]
A copy of XAPP710: "RLDRAM II Controller Using Virtex-4 Devices" and the
corresponding reference design RTL code are included on the CD shipped with the ML461
Tool Kit. For a complete list of FPGA #4 signals and their pin locations, refer to
A, "FPGA Pinouts."
26
describes all signals associated with RLDRAM II memories.
Bits
23 RLDRAM II Address
2 RLDRAM II Differential Clock
2 RLDRAM II Differential Clock
7 RLDRAM II Control Signals
1 RLDRAM II Control Signals
24 RLDRAM II Data and Strobes: Bytes 1:0
24 RLDRAM II Data and Strobes: Bytes 3:2
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Description
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
R
Bank Schematic
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Appendix