Xilinx Virtex-4 ML461 User Manual page 77

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Table A-4: FPGA #4 Pinout (Continued)
Signal Name
RLD2_DQ_BY1_B0
RLD2_DQ_BY1_B1
RLD2_DQ_BY1_B2
RLD2_DQ_BY1_B3
RLD2_DQ_BY1_B4
RLD2_DQ_BY1_B5
RLD2_DQ_BY1_B6
RLD2_DQ_BY1_B7
RLD2_DQ_BY1_B8
RLD2_DQ_BY2_B0
RLD2_DQ_BY2_B1
RLD2_DQ_BY2_B2
RLD2_DQ_BY2_B3
RLD2_DQ_BY2_B4
RLD2_DQ_BY2_B5
DBG_LED0
DBG_LED1
DBG_LED2
DBG_LED3
DBG_LED4
DBG_LED5
CPLD_0
CPLD_1
CPLD_2
CPLD_3
CPLD_CLK
CPLD_DGATE_EN
CPLD_GSR
CPLD_4
CPLD_5
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
RLDRAM II Memory Interface (cont'd)
E9 RLD2_DQ_BY2_B6
F9 RLD2_DQ_BY2_B7
F8 RLD2_DQ_BY2_B8
G8 RLD2_DQ_BY3_B0
B7 RLD2_DQ_BY3_B1
C7 RLD2_DQ_BY3_B2
A9 RLD2_DQ_BY3_B3
B9 RLD2_DQ_BY3_B4
A3 RLD2_DQ_BY3_B5
C17 RLD2_DQ_BY3_B6
D17 RLD2_DQ_BY3_B7
C20 RLD2_DQ_BY3_B8
B20 RLD2_READ_VALID_LOOPBACK_BANK5
B18 RLD2_READ_VALID_LOOPBACK_BANK5
A18
Z-DOK+ Connector Interface
M24 CPLD_6
L26 CPLD_7
M26 CPLD_8
M21 CPLD_9
M20 CPLD_10
M23 CPLD_11
J21 CPLD_12
J20 CPLD_13
J23 CPLD_14
J22 CPLD_15
T24 CPLD_16
U23 CPLD_17
V23 LVDS_TX0
K22 LVDS_TX1
K21 LVDS_TX2
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FPGA #4 Pinout
Signal Name Pin
E17
F17
C21
C19
D18
B24
B23
F18
E18
A20
A19
D22
HD25
HD26
J26
J25
L19
K20
L21
L20
K24
K23
K26
K25
M19
N19
J7
J6
J5
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