Xilinx Virtex-4 ML461 User Manual page 104

Appendix B: LCD Interface
Position
Register
DataIn
8
Ena
E
Rst
Clk
E
Counter B
Clk
A state machine manages the processing order.
A minimum cycle time of 400 ns on the E signal used as a reference. The 200-MHz system
clock frequency is used as reference system clock. One E cycle uses at least 80 system clock
cycles when the design is running at 200 MHz. The E pulse is part of the state machine, and
the design only depends on the system clock. Timing is met as long as the system clock
does not exceed 200 MHz.
This design can be adapted easily to fit the MicroBlaze™ processor or IBM PowerPC
core connect bus system.
104
DesRst
Counter A
11
E
3
L
Display
Clk
Register
DesRst DesRst
Load
TC
Count to 8.
Stop both counters at TC.
Send character position and
DesRst
line to the LCD.
Load new value in counter A.
Switch to character ROM.
Enable counters.
Figure B-11: LCD Character Generator Controller
www.xilinx.com
Page
DI
11
DO
Addr
Ena
DesRst Ssr
RAMB16_S9
We
Clk
DesRst
Rst
Ena
State Machine
Clk
Virtex-4 ML461 Development Board User Guide
8
Data
0
8
8
1
Clk
LUT-ROM
Display
Initialization
RS
RW
E
ug079_b_11_081005
UG079 (v1.1) September 5, 2007
R
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