External Interfaces; Internal Interfaces - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

DMA Controller Overview

External Interfaces

The DMA does not connect external memories and devices directly.
Rather, data is passed through the EBIU port. Any kind of device that is
supported by the EBIU can also be accessed by peripheral DMA or mem-
ory DMA operation. This is typically flash memory, SRAM, SDRAM,
FIFOs, or memory-mapped peripheral devices.
Handshaking MDMA operation is supported by two MDMA request
input pins,
DMAR0
the MDMA0 destination channel. The
channel of MDMA1. With these pins, external FIFO devices, ADC or
DAC converters, or other streaming or block-processing devices can use
the MDMA channels to exchange their data or data buffers with the
Blackfin processor memory.
Both pins reside on port F and compete with UART0 signals. To
DMARx
enable their function, set the
and/or bits in the
PF1
HMDMAx_CONTROL
ing or rising edges of the connect strobe.

Internal Interfaces

Figure 2-1 on page 2-3
dedicated DMA buses used by the DMA controller to interconnect L1
memory, the on-chip peripherals, and the EBIU port.
The 16-bit DMA Core Bus (DCB) connects the DMA controller to a ded-
icated port of L1 memory. L1 memory has dedicated DMA ports featuring
special DMA buffers to decouple DMA operation. See the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference for a
description of the L1 memory architecture. The DCB bus operates at core
clock ( ) frequency. It is the DMA controller's responsibility to trans-
CCLK
late DCB transfers to the system clock (
5-6
and . The
DMAR1 DMAR0
bit in the
PFDE
register. The
PORTF_FER
register controls whether the
of the "Chip Bus Hierarchy"
ADSP-BF537 Blackfin Processor Hardware Reference
pin controls transfer timing on
pin controls the destination
DMAR1
register and the
PORT_MUX
bit in the respective
REP
inputs trigger on fall-
DMARx
chapter shows the
) domain.
SCLK
PF0