Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 162

Functional Description
If is not part of the descriptor, the previous
DMACFG
(as written by MMR access at startup) control the work unit operation. If
is part of the descriptor, then the
DMACFG
by the MMR access controls only the loading of the first descriptor from
memory. The subsequent DMA work operation is controlled by the low
byte of the descriptor's
the descriptor. The bits
programmed by the MMR access are disregarded.
The and
DMA_RUN
cate the state of the DMA channel. After a write to
and
RUN DFETCH
signaled as a result of loading the first descriptor from memory.
After the above steps, DMA data transfer operation begins. The DMA
channel immediately attempts to fill its FIFO, subject to channel prior-
ity—a memory write (RX) DMA channel begins accepting data from its
peripheral, and a memory read (TX) DMA channel begins memory reads,
provided the channel wins the grant for bus access.
When the DMA channel performs its first data memory access, its address
and count computations take their input operands from the start registers
(
DMAx_START_ADDR
to the current registers (
). Note also that the current registers are not valid until the first
Y_COUNT
memory access is performed, which may be some time after the channel is
started by the write to the
loaded automatically from the appropriate descriptor elements, overwrit-
ing their previous contents, as follows.
•
DMAx_START_ADDR
•
DMAx_X_COUNT
•
DMAx_Y_COUNT
5-24
and by the parameter registers loaded from
DMACFG
,
DI_EN DI_SEL
status bits in the
DFETCH
bits can be automatically set to 1. No data interrupts are
, ,
DMAx_X_COUNT
DMAx_CURR_ADDR
DMA_CONFIG
is copied to
is copied to
DMAx_CURR_X_COUNT
is copied to
DMAx_CURR_Y_COUNT
ADSP-BF537 Blackfin Processor Hardware Reference
DMAx_CONFIG
DMAx_CONFIG
, ,
DMA2D WDSIZE
DMAx_IRQ_STATUS
DMAx_CONFIG
), and write results back
DMAx_Y_COUNT
,
DMAx_CURR_X_COUNT
register. The current registers are
DMAx_CURR_ADDR
settings
value programmed
, and in the value
WNR
register indi-
, the
DMA_
,
DMAx_CURR_