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INTEGRATION TOOLS
absence of the required workarounds will prohibit debug assistance from Intel. The following
list of signals are affected:
PREQ#, TCK, TDI, TDO, TMS, TRST#, INIT#, FLUSH#, STPCLK#, PICCLK, PICD[1:0]#,
LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#,
IGNNE# and A20M#.
Figure 13-10 describes the CMOS probe signals of the LAI562.
From Target
The extra loading of the LAI562 requires stronger pull-up values on the target system.
However, due to the current limitations of some signal drivers, this stronger value may not be
feasible. Calculation of the correct pull-up resistor value for each of the CMOS signals
should include a load analysis based on the pull-up voltage, pull-up voltage tolerance, pull-up
resistor tolerance, V
IH
input timings, etc. The resulting values may conflict.
As a result of the extra loading by the LAI, pull-ups to 2.5V are recommended. The actual
value required by a system may vary, depending on the logic connected and the drive
strength of the signal to the Slot 1 connector. See Table 7-3 for recommended pull-up values.
13-12
Vtt_CMOS = 1.04V
Figure 13-10. LAI Probe Input Circuit
and V
specifications, driver current rating, input current leakage,
IL
Input to
Analyzer
V
REF
CLK
000887
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