Accessing The Tap Logic - Intel Pentium II Developer's Manual

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TEST ACCESS PORT (TAP)
Processor
Test Access
Port
Figure 6-1. Simplified Block Diagram of Processor TAP Logic
6.2.

ACCESSING THE TAP LOGIC

The TAP is accessed through a 1149.1-compliant TAP controller finite state machine. This
finite state machine, shown in Figure 6-2, contains a reset state, a run-test/idle state, and two
major branches. These branches allow access either to the TAP Instruction Register or to one
of the data registers. The TMS pin is used as the controlling input to traverse this finite state
machine. TAP instructions and test data are loaded serially (in the Shift-IR and Shift-DR
states, respectively) using the TDI pin. State transitions are made on the rising edge of TCK.
6-2
Boundary Scan Register
BIST Result
Device Identification
Bypass Register
Control Signals
Instruction Decode
Control Logic
TAP
Controller
Machine
TDO
MUX
Instruction
Register
000940

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