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GTL+ INTERFACE SPECIFICATIONS
V
TT
R
T
Driver
Receiver
V
REF´
®
Pentium II Processor
V
REF
External Resistor/
Divider Network
NOTE: V
is generated on the processor.
REF
Figure 8-1. Example Terminated Bus with GTL+ Transceivers
8.1.1.
System Bus Specifications
It is recommended to have the GTL+ bus routed in a daisy-chain fashion with termination
resistors at each end of every signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the V
approximate the substrate impedance. The valid high and low levels are determined by the
input buffers using a reference voltage called V
Table 8-1 lists the nominal specification for the GTL+ termination voltage (V
reference voltage (V
REF
on the motherboard. It is important that the motherboard impedance be specified and held to
65Ω ±20% tolerance, and that the intrinsic trace capacitance for the GTL+ signal group
traces is known. For more details on GTL+, see AP-585, Pentium
Guidelines (Order Number 243330).
8-2
GTL+ Bus
Driver
Core Logic
V
TT
) should be set to 2/3 V
Receiver
Driver
V
REF´
voltage supply and generally are chosen to
TT
.
REF
for the core logic using a voltage divider
TT
V
TT
R
T
Receiver
V
REF´
Pentium II Processor
000945
). The GTL+
TT
®
II Processor GTL+
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