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µop). Most Intel Architecture instructions are converted directly into single µops, some
instructions are decoded into one-to-four µops and the complex instructions require
microcode (the box labeled Microcode Instruction Sequencer in Figure 2-4). This microcode
is just a set of preprogrammed sequences of normal µops. The µops are queued, and sent to
the Register Alias Table (RAT) unit, where the logical Intel Architecture-based register
references are converted into references to physical registers in P6 family processors physical
register references, and to the Allocator stage, which adds status information to the µops and
enters them into the instruction pool. The instruction pool is implemented as an array of
Content Addressable Memory called the ReOrder Buffer (ROB).
2.2.2.
The Dispatch/Execute Unit
The Dispatch unit selects µops from the instruction pool depending upon their status. If the
status indicates that a µop has all of its operands then the dispatch unit checks to see if the
execution resource needed by that µop is also available. If both are true, the Reservation
Station removes that µop and sends it to the resource where it is executed. The results of the
µop are later returned to the pool. There are five ports on the Reservation Station, and the
multiple resources are accessed as shown in Figure 2-5.
To/From
Instruction Pool
(ReOrder Buffer)
Port 0
Reservatio
Station
Port 1
Port 2
Port 3, 4
Figure 2-5. Inside the Dispatch/Execute Unit
MICRO-ARCHITECTURE OVERVIEW
MMX™
Execution Unit
Floating-Point
Execution Unit
Integer
Execution Unit
MMX
Execution Unit
Jump
Execution Unit
Integer
Execution Unit
Load
Loads
Unit
Store
Stores
Unit
000928
000928
2-5
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